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We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns...
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... shown in Fig.1, our objective in the near future is to fabricate 3D super chip with more than 10 layers including various kinds of chip sizes and devices such as MEMS, bio, and sensor chips in addition to memories and processors by the new chip-to-wafer 3D integration technology. ...
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... employed a fillercontaining thermoset polymer with a CTE of 20 ppm/K. As shown in Fig.10, wafer warpage was little produced by the thermoset polymer with fillers when the thickness of the coated polymer is 70µm. ...
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... edge-chipping was hardly generated by coating with the low-CTE resin. Figure 11 shows photomicrographs of the Si chip array before and after thinning. The Si chips with an initial thickness of 280 µm were thinned to around 30 µm by grinding and rapping. ...
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... following CMP provides the Si chips with a highly smooth surface of 2.2 nm in rms roughness, measured by AFM. The bottoms of buried interconnections with rectangular cross-section are also clearly observed in a magnified high-resolution digital microscopy micrograph in the right side corner of Fig.11. By using these key technologies and repeating the sequence, we can obtain 3D LSI test chips of various sizes. ...
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... using these key technologies and repeating the sequence, we can obtain 3D LSI test chips of various sizes. Figure 12 shows a photomicrograph of the resulting threelayer stacked LSI test chips. As shown in Fig.12(a), the smallest chip (5 × 5 mm 2 ) for the 3rd layer is bonded on the 2nd layer chip (6 × 6 mm 2 ) that is stacked on the largest chip (7 × 7 mm 2 ) for the1st layer. ...
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... 12 shows a photomicrograph of the resulting threelayer stacked LSI test chips. As shown in Fig.12(a), the smallest chip (5 × 5 mm 2 ) for the 3rd layer is bonded on the 2nd layer chip (6 × 6 mm 2 ) that is stacked on the largest chip (7 × 7 mm 2 ) for the1st layer. ...
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... sizes of chips are successfully stacked, as shown in Fig.12(b). The first, second, and third chip thickness is around 30, 40, 90 µm, respectively. ...
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... demonstrated the self-assembly in which the plateaus with square in shape and hydrophilic surface are formed on the surface of a supporting wafer and the test chips with hydrophilic surface are aligned onto the plateaus on the supporting wafer. As shown in Fig.13, aqueous liquid was dropped onto the plateau on the supporting wafer and the test chip was placed on this plateau. ...
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... using the selfassembly, Si chips were precisely aligned by using surface tension of the liquid within 0.1 sec. High alignment accuracy within ±1 µm was obtained, as shown in Fig.14. Chip-towafer 3D integration in batch is realized by this self-assembly process that can provide high-throughput alignment and bonding. ...
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Citations
... Surface tension-driven aggregation was first adopted for the self-assembly of heterogeneous functional systems by the Whitesides' Group [5,47,48]. It was later adapted to part-to-substrate assembly tasks by the teams of Howe [41,42], Böhringer [53], Koyanagi [13,14], Parviz [33,43] and Jacobs [8,57]-to mention but a few examples. 1 Most aforementioned assembly techniques share, at least partly, the same underlying mechanism. ...
... pre-conditioned to enable further processing) side of the part to be assembled (hereby representing e.g. an IC die, a microdevice, a MEMS component) and the highly-energetic mating surfacecomposed by a fluid, such as e.g. hydrocarbons [42], water-based solutions [14] or molten solders [37]-of the corresponding binding site on the substrate, capillary torques 2 and forces-both perpendicular (i.e. vertical) and parallel (i.e. ...
Lateral capillary forces ensuing from perturbed fluid menisci are pivotal to many important technologies, including capillary self-alignment and self-assembly of heterogeneous microsystems. This chapter presents a comprehensive study of the quasi-statics of lateral capillary forces arising from a constrained cylindrical fluid meniscus subjected to small lateral perturbations. After a contextual literature review, we describe a novel experimental apparatus designed to accurately characterize such a fundamental system. We then reproduce our experimental data on lateral meniscus forces and stiffnesses by means of both a novel analytical model and a finite element model. The agreement between our measurements and our models validate earlier reports and provides a solid foundation for the applications of lateral capillary forces to microsystems handling and assembly.
... This can be achieved by making the receptor sites highly wetting and the background non-wetting (e.g. hydrophilic/hydrophobic patterns for water [6][7][8] or oleophilic/oleophobic patterns for oil-like liquids [9]). The non-wettable areas can be made by combining low surface energy chemical treatment (e.g. ...
In this paper, we report capillary self-alignment of 200 ×x 200 μm square parts on matching patterns with undercut edges. The undercut edge structure is a purely topographical feature that provides ultimate pinning for liquids of any surface tension without chemical treatment. We show contact angles close to 180° for low surface tension liquids, and capillary self-alignment using thermally curable adhesive. Submicron alignment accuracy after adhesive curing is verified in a scanning electron microscope (SEM).
... Surface-tension-driven self-assembly was first exploited for the construction of heterogeneous functional systems by the Whitesides Group [15] [16] [17] [18]. It was later optimized and adapted to specific part-to-substrate assembly tasks by Srinivasan [19], Böhringer's group [20], Scott [21], Koyanagi's group [22] [23], Parviz's group [24] [25] and Jacobs' group [26] [27], to mention but a few examples. All aforementioned electronic manufacturing techniques share, at least partly, the same underlying mechanism. ...
... IC die, microdevice, MEMS component) and the highly-energetic mating surface -normally composed by a fluid, such as e.g. hydrocarbons [19], water-based solutions [22] or molten solders [28] -of the corresponding binding site on the substrate, capillary forces -both perpendicular (i.e. axial) and parallel (i.e. ...
Capillarity is pivotal to many important technologies, including capillary self-alignment and self-assembly for heterogeneous microsystem integration and packaging. Lateral capillary forces ensuing from perturbed fluid menisci were the object of substantial theoretical and numerical modeling in recent years. Anyway, those studies were so far unsatisfactorily supported by direct experimental inspections. In this paper we present a comprehensive quasi-static study of lateral capillary forces arising from a constrained cylindrical fluid meniscus subjected to small lateral perturbations. We describe the novel experimental apparatus that we designed to accurately characterize such a fundamental system. We then reproduce our experimental data on lateral meniscus forces and stiffnesses by means of both a finite element and a novel analytical model. The agreement between our measurements and models, while confirming earlier reports, provides a solid foundation for the applications of lateral capillary forces to microsystem assembly. Moreover, our experimental apparatus may enable the exploitation of Gibbs' inequality to measure the advancing contact angles of liquids, and it may be used as a reference testbed for further experimental investigations on constrained fluid menisci.
... Surface-tension-driven self-assembly was first exploited for the construction of heterogeneous functional systems by the Whitesides Group [15][16][17][18]. It was later optimized and adapted to specific part-to-substrate assembly tasks by Srinivasan [19], Böhringer's group [20], Scott [21], Koyanagi's group [22,23], Parviz's group [24,25] and Jacobs' group [26,27], to mention but a few examples. ...
... IC die, microdevice, MEMS component) and the highly-energetic mating surface -normally composed by a fluid, such as e.g. hydrocarbons [19], water-based solutions [22] or molten solders [28] -of the corresponding binding site on the substrate, capillary forces -both perpendicular (i.e. axial) and parallel (i.e. ...
... Self-alignment using the fluidic effect inspired many researches in the precision engineering field3637383940.Figure 8 shows a self-alignment process using liquid surface tension in four following steps: (1) the region where the MEMS chip is aligned is the high wettability area, corresponding to the electrode array of the electronic chip; this region is surrounded by the low wettability area, which is based on fluorocarbon layer deposition; we apply principles of minimum potential energy to operate self-alignment; (2) using water droplets (e.g. from a syringe), we grow a large water droplet into the high wettability region; (3) the MEMS chip is put on the liquid where surface tension and capillary forces are generated to drive it toward its alignment position; (4) the surface tension and capillary forces stabilize the MEMS chip in its alignment position before bonding and electrical contact steps. According to this process, we achieve two selective areas by patterning only one hydrophobic contour area. ...
Nowadays, industries are investigating new, original and appropriate solutions to address challenges in 3D MEMS-IC large-scale integration. Self-assembly techniques are among those. We report on an alternative approach inspired from fluidic self-assembly and using the flip-chip method. Here, solder bumps are directly formed onto a MEMS chip using liquid solder solution in a bath. The self-alignment process is operated after surface treatment by plasma deposition to form high and low wettability selective patterns. Finally, MEMS and electronic chips are permanently bonded after low thermal heating without any pressure. Electrical contact is established and electromechanisms of the microsystems are proven. Compared to classic MEMS-IC flip-chip methods, this strategy presents many advantages: it is a low-cost and fast fabrication process requiring no specific equipment for deposition of solder bumps. Furthermore, it can be applied on different substrates and it does not require a specific pressure method during the bonding process. This strategy is also an appropriate fabrication method for large-scale MEMS integration where electronic connection density is high.
... However, when chips are bonded as arrays on a wafer, the process has to be repeated as many times as the number of laminated chips in the array. If precise alignment accuracy is required, the process time for stacking each layer increases further [17]. Thus, because of the low expected fabrication throughput, chip-to-chip and chip-to-wafer bonding techniques may not ultimately be cost effective. ...
Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.
... Xiong et al [4] used a polymer for capillary alignment and mechanical binding of LEDs to the substrate, and post-assembly electroplating of solder vias for electrical interconnects, thus requiring extensive postprocessing and dedicated substrate structures. Fukushima et al. [5] enhanced pick-and-place with capillary selfalignment of dies for wafer reconstruction on a temporary carrier, followed by wafer-level alignment and transfer of dies to the target substrate, and substantial post-processing to realize electrical connections. In molten-solder-driven SA [6] the high surface tension of a molten solder is used, normally in combination with die/substrate geometric shape-matching, to drive the assembly of components and establish, at the same time, electrical and mechanical interconnects. ...
Capillary fluidic self-assembly (SA) intrinsically features massively-parallel, contactless die handling and allows for high-precision die placement. It may thus boost die-to-substrate assembly throughput and scalability. Here we characterize for the first time indium interconnects established between dummy dies and substrates as integral part of a capillary SA process. We present a simple way to keep the solder surface free of oxide during assembly, and we show that In/Au wetting and bonding is not prevented by hydrocarbons and self-assembled monolayers locally present during processing. Resulting solder joints are characterized by mechanical shear tests, SEM and SAM. We assess the electrical functionality of interconnects with a simple test structure. Finally, we discuss the effects of an external load applied on dies during bonding. Our results open interesting perspectives for adopting capillary SA for die integration over non-planar substrates.
