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Structure of 3D super chip

Structure of 3D super chip

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Conference Paper
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We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns...

Contexts in source publication

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... shown in Fig.1, our objective in the near future is to fabricate 3D super chip with more than 10 layers including various kinds of chip sizes and devices such as MEMS, bio, and sensor chips in addition to memories and processors by the new chip-to-wafer 3D integration technology. ...
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... employed a fillercontaining thermoset polymer with a CTE of 20 ppm/K. As shown in Fig.10, wafer warpage was little produced by the thermoset polymer with fillers when the thickness of the coated polymer is 70µm. ...
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... edge-chipping was hardly generated by coating with the low-CTE resin. Figure 11 shows photomicrographs of the Si chip array before and after thinning. The Si chips with an initial thickness of 280 µm were thinned to around 30 µm by grinding and rapping. ...
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... following CMP provides the Si chips with a highly smooth surface of 2.2 nm in rms roughness, measured by AFM. The bottoms of buried interconnections with rectangular cross-section are also clearly observed in a magnified high-resolution digital microscopy micrograph in the right side corner of Fig.11. By using these key technologies and repeating the sequence, we can obtain 3D LSI test chips of various sizes. ...
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... using these key technologies and repeating the sequence, we can obtain 3D LSI test chips of various sizes. Figure 12 shows a photomicrograph of the resulting threelayer stacked LSI test chips. As shown in Fig.12(a), the smallest chip (5 × 5 mm 2 ) for the 3rd layer is bonded on the 2nd layer chip (6 × 6 mm 2 ) that is stacked on the largest chip (7 × 7 mm 2 ) for the1st layer. ...
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... 12 shows a photomicrograph of the resulting threelayer stacked LSI test chips. As shown in Fig.12(a), the smallest chip (5 × 5 mm 2 ) for the 3rd layer is bonded on the 2nd layer chip (6 × 6 mm 2 ) that is stacked on the largest chip (7 × 7 mm 2 ) for the1st layer. ...
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... sizes of chips are successfully stacked, as shown in Fig.12(b). The first, second, and third chip thickness is around 30, 40, 90 µm, respectively. ...
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... demonstrated the self-assembly in which the plateaus with square in shape and hydrophilic surface are formed on the surface of a supporting wafer and the test chips with hydrophilic surface are aligned onto the plateaus on the supporting wafer. As shown in Fig.13, aqueous liquid was dropped onto the plateau on the supporting wafer and the test chip was placed on this plateau. ...
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... using the selfassembly, Si chips were precisely aligned by using surface tension of the liquid within 0.1 sec. High alignment accuracy within ±1 µm was obtained, as shown in Fig.14. Chip-towafer 3D integration in batch is realized by this self-assembly process that can provide high-throughput alignment and bonding. ...

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Citations

... Surface tension-driven aggregation was first adopted for the self-assembly of heterogeneous functional systems by the Whitesides' Group [5,47,48]. It was later adapted to part-to-substrate assembly tasks by the teams of Howe [41,42], Böhringer [53], Koyanagi [13,14], Parviz [33,43] and Jacobs [8,57]-to mention but a few examples. 1 Most aforementioned assembly techniques share, at least partly, the same underlying mechanism. ...
... pre-conditioned to enable further processing) side of the part to be assembled (hereby representing e.g. an IC die, a microdevice, a MEMS component) and the highly-energetic mating surfacecomposed by a fluid, such as e.g. hydrocarbons [42], water-based solutions [14] or molten solders [37]-of the corresponding binding site on the substrate, capillary torques 2 and forces-both perpendicular (i.e. vertical) and parallel (i.e. ...
Chapter
Lateral capillary forces ensuing from perturbed fluid menisci are pivotal to many important technologies, including capillary self-alignment and self-assembly of heterogeneous microsystems. This chapter presents a comprehensive study of the quasi-statics of lateral capillary forces arising from a constrained cylindrical fluid meniscus subjected to small lateral perturbations. After a contextual literature review, we describe a novel experimental apparatus designed to accurately characterize such a fundamental system. We then reproduce our experimental data on lateral meniscus forces and stiffnesses by means of both a novel analytical model and a finite element model. The agreement between our measurements and our models validate earlier reports and provides a solid foundation for the applications of lateral capillary forces to microsystems handling and assembly.
... This can be achieved by making the receptor sites highly wetting and the background non-wetting (e.g. hydrophilic/hydrophobic patterns for water [6][7][8] or oleophilic/oleophobic patterns for oil-like liquids [9]). The non-wettable areas can be made by combining low surface energy chemical treatment (e.g. ...
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... Surface-tension-driven self-assembly was first exploited for the construction of heterogeneous functional systems by the Whitesides Group [15] [16] [17] [18]. It was later optimized and adapted to specific part-to-substrate assembly tasks by Srinivasan [19], Böhringer's group [20], Scott [21], Koyanagi's group [22] [23], Parviz's group [24] [25] and Jacobs' group [26] [27], to mention but a few examples. All aforementioned electronic manufacturing techniques share, at least partly, the same underlying mechanism. ...
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