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Standby-SRAM architecture: Let B k 1 be the data vector to be stored. Then B k 1 is encoded into U n 1 and stored in n memory cells. The i th stored bit is stuck-at Si if DRVi ≥ vS, otherwise Ui is read-out. The decoder reads Y n 1 and outputs B k 1 . The voltage vS is selected such that P(outage) negligible (see (2)).
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We study the problem of reducing power during data-retention in a standby static random access memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be greater than a critical data retention voltage (DRV). Due to circuit parameter variations, the DRV for different cells on the same chip exhibits variation with a di...
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The authors study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above which it preserves the stored-bit reliably. Due to process-variations, the intra-chip DRV exhibits variation with a distribution having a diminishing tail. In order to minimiz...
FPGAs are a ubiquitous electronic component utilised in a wide range of electronic systems across many industries. Almost all modern FPGAs employ SRAM based configuration memory elements which are susceptible to radiation induced soft errors. In high altitude and space applications, as well as in the nuclear and defence industries, such circuits mu...
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... For reducing the leakage current, power supply voltage is reduced due to which SNM invariably decreases [8], [10]. So to balance this trade off for appropriate performance, a development of a device/technology is desirable that can give higher cell stability and reduce leakage power consumption [11] - [13]. In this regard, a double gate MOSFET is suited as it serves to control channel by the two gates and thus helps in reducing the leakage current and overcoming other short channel effects as it provides better coupling due to the presence of two gates. ...
In recent technologies, device scaling leads to increase in dynamic power, sub threshold leakage, and degradation of noise margins which are vital obstacles in future generation memory circuits. This paper explores the design of a 6T cell of SRAM. A low power, large SNM 6T cell using conventional MOSFET and DG MOSFET is designed and the results of simulation using ATLAS shows that a 6T cell using DG MOSFET gives better performance compared to conventional MOSFET in terms of SNM even at low supply voltages down to 0.3V.
... First we discuss the case when T S → ∞, i.e., E C contribution is normalized to zero. In this case, for n large and negligible decoding failure probability, it has been shown that [7], ...
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free V<sub>DD</sub> to 155 mV. With a 100 mV noise margin, a 255 mV standby V<sub>DD</sub> effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V V<sub>DD</sub>.
... Minimization of power per bit results in a supply-voltage at which a small fraction of cells fail to retain the data. For experimental a [31, 26,3] Hamming code based implementation achieves a significant portion of the leakage power reduction compared to the fundamental limit. These analytical results are verified by twenty-four experimental chips manufactured in an industrial 90nm CMOS process. ...
... The DRV max with supply-noise margin is the supply voltage for the worst-case strategy (say v max ). For power reduction below the worst-case strategy, a supply voltage lower than v max , with appropriate error-control coding to overcome ensuing errors, was proposed [3]. Under this approach, with the supply-voltage flexible and the DRV distribution as in Figure 1, it was shown that the leakage power per useful bit can be (fundamentally) reduced by approximately 40% (with respect to power consumption at supply voltage v max ), while taking coding power overhead into account. ...
... Row-redundancy with initial testing can be used to fix these decoding failures. By choosing v S large-enough (but less than v max ), 1% rows were expected to fail due to multiple retention failures [3]. ...
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parameter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. The DRV exhibits significant intra-chip variation in the deep sub-micron era. As supply voltage is lowered, leakage power reduces, but a larger fraction of SRAM cells is prone to retention failures. Use of appropriate error-correction to mitigate cell- reliability is proposed. Using this approach, the standby supply voltage is selected to minimize leakage power per useful bit. The fundamental limits on the leakage power per useful bit, while taking the DRV distribution into account, are established. Minimization of power per bit results in a supply-voltage at which a small fraction of cells fail to retain the data. For experimental DRV -distributions, a [31,26,3] Hamming code based implementation achieves a significant portion of the leakage power reduction compared to the fundamental limit. These analytical results are verified by twenty-four experimental chips manufactured in an industrial 90 nm CMOS process.
With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
