Speed Comparison (16 bit 16-taps)

Source publication

Figure 1. Block diagram of TOP module of the FIR Filter

Figure 4. Implementation of FIR filter using DA

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

Article

Full-text available

Jul 2016

P. Hemanthkumar
Y. Sai Kiran
V. Nava Teja

p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address lengt...