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Canonic signed digit (CSD) recoding finds applications in real time VLSI signal processing. In this paper, we have proposed optimized FPGA implementations of CSD recoding techniques starting from a two’s complement input and a redundant signed digit (SD) input. The architectures exploit the fast, hardwired fabric resources of the FPGA logic element...
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Probabilistic-based methods have been used for designing noise-tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in c...
Citations
... The reliability of the system is defined as the probability of obtaining the correctly processed message at the output [10,11]. To derive a general expression for the reliability of the system, we use an adapted from the total probability as translated into the language of reliability. ...
Fault-tolerance is the property that enables a system to continue operating properly in the event of the failure of (or one or more faults within) some of its components. Fault-tolerance is particular sought after in high-availability or life-critical system. A fault tolerant design enables a system to continue its intended operation possibly at a reduced level, rather than falling completely, when some part of the system fails. In this paper we discuss the redundancy optimal system size with the reliability evaluation of a system of components.
Signed-digit number system is an unconventional number system which has been found to cause greater efficacy and efficiency in performing some arithmetic operations. Obviously, it seems interesting to investigate signed-digit number system in wider context, including designing magnitude comparator. Although magnitude comparator is an integral part of every standard arithmetic processor, no significant work on magnitude comparison has been reported yet even for the more propitious categories of signed-digit number system, including canonical signed-digit number system. In this paper, an algorithm for magnitude comparison of canonical signed-digit number system is proposed in terms of comparing the magnitudes and signs of some counterpart portions of the inputs. The proposed algorithm can be immediately implemented at hardware level employing some ordinary logic gates only and in every execution stage of the proposed algorithm, all operations may be completed in a fairly small number of logic levels.
Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.
In this paper, we have achieved run-time dynamic reconfiguration by employing a category of logic cells equipped to realize programmability in Cellular Automata (CA) architectures on Field Programmable Gate Arrays (FPGAs). This is essential for real time VLSI implementations of random number generators, whose functionality requires reconfiguration during run-time, and are called Programmable CA (PCA). The logic cells realizing the PCA are amongst a subset of Look-Up Tables (LUTs) offered by Xilinx FPGAs, known as CFGLUT5. Programmability involves scanning out the contents of the truth-table (TT) originally configuring these LUTs and reconfiguring it with a modified functionality. This feature additionally aids testability which allows to carry out an equality check of the scanned output with a golden copy of the TT contents originally configuring the LUTs during design deployment. Vacant inputs in the LUTs realizing the PCA have been used to establish different scan path arrangements through flip-flops for exercising testability and fault localization further. The entire design flow resulted in a no logic overhead scenario compared to where scan paths did not exist. Any physical FPGA slice coordinate housing a faulty logic element, can be suitably bypassed for future implementations on the same FPGA by applying appropriate placement constraints.
