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A genetic algorithm (GA) is an optimization method based on natural selection. Genetic algorithms have been applied to many hard optimization problems including VLSI layout optimization, boolean satisfiability, power system control, fault detection, control systems, and signal processing. GAs have been recognized as a robust general-purpose optimiz...
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... the FPGAs on the BORG board were too small for the entire HGA design, additional FPGAs were inserted into the BORG board's prototyping area and connected to the BORG FPGAs. The BORG's prototyping area was used to support the tness, selection, and memory interface and control modules (Fig. 4). The population sequencer shared an FPGA with the memory interface and control module. The prototyping area had three XC4005s wire-wrapped to each other and to the chips on the BORG board. If the desired tness function is not the default programmed in the tness module (f(x) = x was our default), the user can place other FPGAs in the ...
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Citations
... Therefore, in this work, besides software implementation, hardware implementations are studied and evaluated. It is clear that the area required by this work is more than [5,15,16]. From another respective, our proposed hardware is faster than [1,15] and also approximately is faster than [16]. The main advantage of proposed approach over [15,16] is applying almost all of the ...
... It is clear that the area required by this work is more than [5,15,16]. From another respective, our proposed hardware is faster than [1,15] and also approximately is faster than [16]. The main advantage of proposed approach over [15,16] is applying almost all of the ...
... From another respective, our proposed hardware is faster than [1,15] and also approximately is faster than [16]. The main advantage of proposed approach over [15,16] is applying almost all of the ...
Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only don’t this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.
... For the realization of these two types of EHW, the all need a common platform to run evolutionary algorithms, that is to say need the kernel, which adapt to the evolutionary computation. In Paper [4][5][6], people are study the evolution environment based on the programmable devices, through its integration into the standard system, providing the "evolution " features. Tommisksa and Vuori [4] designed the genetic algorithm based on Altera 10K series FPGA . ...
There are some problems in the implementation of adaptive systems, which are the design complexity related to the problems. In this paper, through analyze the structure of adaptive systems, we divide the evolutionary system into two parts, one is the evolutionary algorithms kernel and the other is the fitness calculator. In the implementation process, the evolutionary algorithms kernel is implementation using the state machine which described by VHDL language, and the population size, the length of chromosome and other parameters can be configured. We implement the kernel based on Xilinx Virtex-V1000FG680 and use the test problem to verify the effectiveness of our design. (c) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]
... Scott et al. described a fully functional hardware based genetic algorithm [12] in VHDL, designed to act as a coprocessor with the CPU of a PC. It was implemented on a prototyping board called BORG, which contained five Xilinx FPGAs. ...
... The fitness evaluation component was implemented on a neural network [13] making the entire architecture problem independent, generic and massively parallel. The architecture was programmed into SPARTAN3 Xilinx FPGA [15] and was found to be more than 5 times faster than the SGA developed by Scott et al [12], but it occupied twice the area. Wakabayashi et al. developed a new GA Accelerator (GAA) [17] where the crossover operator to be applied to each individual was dynamically selected during algorithm execution. ...
Genetic algorithms (GAs) are intelligent search techniques based on the theory of evolution. Software GAs typically require a long processing time. The inherent parallelism in GAs motivates their implementation in hardware. This project extends an existing library of GA hardware modules and performs a comparative analysis of performance for various module choices. A sample architecture developed using the modules is applied to DNA sequence alignment and its performance is compared with the standard software algorithm ClustalW.
... Analyses of GA/EC strategies indicate, however, that about 80-90% could be reduced by parallel execution of its simple reproduction operators. Therefore dedicated FPGA solutions are feasible and already proposed [31]. ...
Computational intelligence and its applications have been under dynamic development in the last years. The research areas as fuzzy logic, neural networks or evolutionary computation have demonstrated their power on a large amount of problems, e.g. in pattern recognition, system control, system diagnosis, and intelligent signal processing. We give a short review of the developments in this area over the last years. We show here that a developer of dedicated hardware should be aware of the problems in developing specialized hardware for computational intelligence, i.e. he has to compete with mainstream microcomputer implementations of the same techniques. Furthermore we point out some directions for promising research and possibilities for system improvements, especially in the area of neural network algorithm and system research
... Due to the computational intensity and abstract nature of the stages involved in Genetic Algorithms, attempts have been made to extend the applications of Genetic Algorithms into the hardware domain. FPGA's (Field Programmable Gate Arrays) [2][3] [5] [8] are re-configurable chips that offer a good platform on which different architectures can be investigated before designing a dedicated hardware chip. The design of a hardware system can be written behaviorally in a Hardware Description Language and downloaded into the FPGA for further analysis. ...
... Scott, Seth and Samal, [5] attempted to create a hardware-based Genetic Algorithm where a personal computer communicated with an evolutionary process running on programmable application specific hardware. In their system, the personal computer interacted with the evolutionary process via shared memory. ...
"A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science in Department of Electrical and Computer Engineering." Thesis (M. Sc.)--University of Alberta, 2003. Includes bibliographical references.
In this chapter,we propose a massively parallel architecture of a hardware implementation of genetic algorithms. This design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimises the required hardware area without much increase in response time. Last but not least, we demonstrate the characteristics of the proposed hardware and compare it to existing ones.
Genetic Algorithms (GAs) following a parallel master-slave architecture can be effectively used to reduce searching time when fitness functions have fixed execution time. This paper presents a parallel GA architecture along with two accelerated GA operators to enhance the performance of master-slave GAs, specially when considering fitness functions with variable execution times. We explore the performance of the proposed approach, and analyse its effectiveness against the state-of-the-art. The results show a significant improvement in search times and fitness function utilisation, thus potentially enabling the use of this approach as a faster searching tool for timing-sensitive optimisation processes such as those found in dynamic real-time systems.
The main target of this chapter is to present the intrinsic evolvable hardware structures: concept, design and applications. The intrinsic evolvable hardware structures concept join more research areas like: bio-inspired searching methods evolutionary algorithms, optimization of algorithms by parallel processing and reconfigurable circuits. First, a general overview about intrinsic evolvable hardware structure is presented. The intrinsic evolvable hardware structure consists in two main modules: hardware genetic algorithm and dynamic reconfigurable circuit. In a particular application, the hardware genetic algorithm searches the configuration that makes the reconfigurable circuit to correctly respond to application requirements. In a background section are presented the genetic algorithm concept as a bio-inspired search solution, the hardware reconfiguration concept with sub areas classifications and the research directions in the evolvable hardware structures areas with application examples. In the first part of the main section are presented the design solutions for hardware implementation of genetic algorithm. Then the solutions are presented for the reconfigurable circuit design and interconnection between reconfigurable circuit and hardware genetic algorithm. Finally, are presented several applications that illustrate the usefulness of the intrinsic evolvable hardware structure. Intrinsic evolvable hardware can be used as a method of resolving faults occurring in some parts of the digital circuit.
Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only don’t this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.
Neural computing, fuzzy logic and evolutionary computing are widely used in a broad range of application fields. While many fields take full advantage from conventional von Neumann processors, there are still classes, such as for example intelligent systems in high-energy physics, requiring the speed of fully hardware implementations. In the first part of this chapter, we discuss the hardware specifications of intelligent systems. These are outlined as basic specifications (including external input/output architecture, topology for neural networks or defuzzification function for fuzzy systems), hardware specifications (including the technology and the precision required), and performance specifications. These specifications are mapped over existing architectures such as general purpose (micro controllers and digital signal processors, extended instruction set architectures and coprocessors), and dedicated ones. Further, we review a sample of various VLSI implementations including digital and analog. We also investigate a selection of basic building blocks suitable for neural networks, fuzzy logic and genetic algorithms.
