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... block diagram of an overall system is depicted in Fig. 1. Here unbalance is created by simulating the symmetrical and asymmetrical ...
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... the three phase source voltage. It becomes unbalanced, during fault conditions as shown in Fig. 1. Positive sequence reference voltage controlled series compensator is connected in the power system, in order to prevent unbalance at the load side. Under unbalance condition, there exists positive, negative and zero sequence components. In a balanced system, positive sequence component alone exist.Thus to obtain balanced load voltage ...
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... comply with the grid code requirements. Moreover, as stated in [17], it cannot avoid phase jumps at the fault occurrence. This is the case as the method is only proven to be effective provided that the voltages at the PCC are not exposed to any phase jumps at the fault instant and that the frequency can be considered constant during the fault. ...
As grid-connected converters are at risk of losing synchronism with the grid when exposed to extreme voltage sags, this might jeopardize the stability during a fault and a converter's ability to comply with fault ride-through requirements. This paper investigates the synchronization stability of grid-tied converters during severe symmetrical faults with phase jumps. To achieve zero-voltage ride-through capability, a frozen PLL structure can be employed to guarantee stability during faults. However, as the frozen PLL approach is unaware of frequency drifts and phase-angle jumps in the grid voltage, its performance during non-constant frequency and phase is unknown. Therefore, this paper investigates and provides new insight into how the frozen PLL performs during phase jumps and reveals whether phase compensation should be utilized to improve the converter response during a severe symmetrical fault. It is disclosed, that even though phase compensation can improve the injected currents during a fault situation including large phase jumps, a non-compensated frozen PLL can inherently ensure stability and allow for zero-voltage ride-through capability at an acceptable current injection. Furthermore, the robustness of the frozen PLL has been analyzed through a comprehensive simulation study where three test cases have been experimentally verified, which confirms the presented findings.
