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This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip s...
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... DELTA-SIGMA MODULATOR AND GAIN CONTROL Fig. 3 shows the simplified schematic diagram of the third- order delta-sigma modulator, without the gain-and offset-con- trol circuits. It uses a low-distortion configuration, in which the SC integrators (ideally) do not carry the input signal, so that the required linearity of the operational amplifiers (opamps) is re- duced [6, ch. 3]. ...
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... and the digital section, which reduce the digital noise coupling into the sensitive input stage. The chip occupies an area of 1.59 1.31 mm . Typical measurement results are shown in Fig. 10 for the output noise, Fig. 11 for integral nonlinearity (illustrating the very small tem- perature coefficient), and Fig. 12 for the supply current. Figs. 13 and 14 show the distributions of the offset and gain errors, re- spectively, obtained from measurements performed on 50 parts at different temperatures. As Fig. 13 illustrates, the offset is typ- ically around 2 V. This is consistent with the 22-bit resolution. As a comparison, some chopper-stabilized instrumentation am- plifiers achieved 0.2 ...
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... results are shown in Fig. 10 for the output noise, Fig. 11 for integral nonlinearity (illustrating the very small tem- perature coefficient), and Fig. 12 for the supply current. Figs. 13 and 14 show the distributions of the offset and gain errors, re- spectively, obtained from measurements performed on 50 parts at different temperatures. As Fig. 13 illustrates, the offset is typ- ically around 2 V. This is consistent with the 22-bit resolution. As a comparison, some chopper-stabilized instrumentation am- plifiers achieved 0.2 V input-referred offset voltage [11]. How- ever, chopper-stabilized delta-sigma ADCs have typically much higher offset values (ranging from 10 V in [12] to ...
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Citations
... The IDSC used for simulation is shown in Fig. 9 [14]. The circuit uses the standard 0.18μm CMOS process, at a sampling frequency of 1.024MHz with a bandwidth (BW) of 2kHz and the V ref is 1.8V. ...
This paper introduces a novel algorithm for optimizing the coefficients of the digital filters used in incremental delta-sigma analog-to-digital converters (IDSC). This algorithm is modified from constrained linear least squares (LS) to improve the signal-to-noise-and-distortion ratio (SNDR) of IDSC and minimize the oversampling rate (OSR) of the modulator, which enhances system speed and reduces power consumption. In the case of the same SNDR, the first-order IDSC with the proposed filter can reduce the OSR of the modulator by 50%, at least compared to the IDSC with the conventional filter. The second-order IDSC with the proposed filter can reach a higher SNDR of 106 dB with an OSR of 64. Considering the nonlinearity of the integrator, the SNDR of IDSC with the proposed filter is also 10 dB greater than that of the conventional filters and 3dB greater than that of the IDSC using the near-optimal algorithm filter. The experimental results indicate that the proposed filter possesses an excellent figure of merit of 0.028 pJ/conv\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\textrm{pJ}/\textrm{conv}$$\end{document}.
... Apart from achieving reconfigurable resolution, various high resolution ADCs have been introduced in the literature. A 22 bit 3rd order single loop incremental ADC was presented in [54] for instrumentation and measurement applications. Also, a 20 bit incremental zoom-ADC has been given in [55]. ...
We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.
... For first-order SDMs, the above up-modulated residual offset can be easily removed by a low-pass filter. However, for second-order SDMs, the residual offset generated from the first stage will be accumulated at the second integrator, similarly with the accumulation of the offset generated from the operational amplifier in the first stage [29]. ...
This Letter presents a low-residual-offset second-order sigma-delta modulator. By inserting a chopper working at low frequency to the mirrored integrator at the first stage of the modulator, the original residual offset is transferred to a high frequency, which can be removed by the filter. Besides, by applying the second-order fractal sequence as the timing of the new added chopper, the residual offset accumulation problem due to the integration at the second stage can be avoided. To evaluate the effect of residual offset suppression conveniently, a programmable timing is integrated to the design to control the state of the added chopper. The presented modulator is fabricated in a 0.18 um CMOS technology, the core area of which is 0.38 mm². Based on the measurement results, the DC offset of the sigma-delta modulator with the proposed method is reduced by 85.6 μV. The modulator realizes 64.8 dB dynamic range with 1 MHz sampling rate, which consumes 0.96 mW from a 3.3 V supply.
... The induced noisefolding in the auto-zeroing phase will inevitably increase the near-DC noise floor, which sets the input sampling capacitor requirement. Systemlevel chopping at 250 Hz further lowers the residual offset [133,194]. ...
... Compared with the design proposed by Chen et al. [19], we note that, while the bandwidths of the input signal are similar, the first-order integrator design adopted in the present study employs an op amp with a higher accuracy, better noise suppression effect, and higher SNR. The design proposed by Quiquempoix et al. [20] achieved a higher SNR than the presently proposed design, but the presently proposed design employed a lower order integrator, and therefore provides lower power consumption. Finally, compared with the designs proposed by Agah et al. [18] and Garcia et al. [21], the current design not only achieved a higher SNR, but also a smaller chip area. ...
In this study, an IDC applicable for use with temperature and humidity sensors was designed. To this end, we take into account the factors of area and accuracy, a simple second-order chain of integrators with forward (CIFF) architecture was used to achieve an effective number of bits (ENOB) of 16.5. A gain-boosted operational amplifier (op amp) with a gain of up to 145 dB was adopted for the first-order integrator, and the digital filter adopted a sinc L structure. In Section 2.1, the working principle of the proposed second-order. IDC is introduced. In Section 2.2, the design specifications are presented, the system timing and circuit structure are introduced, the circuit structure of the first-order integrator is described in detail, and the overall simulation results are provided. In Section 3, the test results obtained for a physical chip implemented using the SMIC 0.18 μm process are presented and compared with those obtained by similar previously proposed designs. Measurements show that the incremental converter achieves 99.1 dB SNR higher than the other second-orders or even some three-order IDC. And the chip occupied an effective area of 0.211 mm ² smaller than the other IDC. Finally, the conclusions of this study are given in Section 5.
... The measured power consumption of the analog circuit is 760μW at a supply voltage of 3.3V, and the digital decimation filter consumes 100μA currents under 1V. Table I compares this work with other state-of-the-art high resolution ADCs [28], [29], [30]. The figure-of-merit (FOM) can be calculated as follow [20]: ...
This paper presents a low-power high-precision sigma-delta analog-to-digital converter (ADC) mainly used for DC measurement, especially in applications with high input impedance. A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. Furthermore, it also improves noise performance in the first integrator. The 1.17 mm² chip is fabricated in a standard 65nm CMOS process. Measurement results show that the ADC achieves 20-bit resolution, 10ppm INL and a 0.6μV offset, while consuming 860μW from 3.3V supply.
... For applications of low/medium PR, e.g., 100 kHz, to achieve a 12-bit ENOB [37], it is a good practice to incorporate a single-bit quantizer [34], [38] in the IDSM due to the following advantages that it has. First, it is unconditionally linear; second, it makes the design of the succeeding decimation filter easier; finally, it has mismatch-immunity and low power. ...
Correlated double sampling (CDS) circuits are essential to processing the X-ray charge-coupled devices (CCDs) that have been used in the modern X-ray astronomical field. For spectroscopy observations, the energy resolution is of decisive importance. In this paper, a comprehensive study of the CDS algorithm based on the incremental ΔΣ technique, named ΔΣ-CDS algorithm hereafter, is studied. Theoretical and practical aspects for modulations and demodulations for applications with different pixel rates (PRs) are discussed. The concepts of differential cascade-of-integrator filter and truncated cascaded-integrator-comb filter are extensively investigated from both the time-domain and frequency-domain analyses. The operating principles, prototype design, and experimental results are addressed. As a prototype for 100-kHz PR, a readout integrated circuit (ROIC) is designed. When tested with the target X-ray CCD-CCD236 using a 1 μCi
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Fe radioisotope, the ROIC achieves an energy resolution characterized by the full-width-at-half-maximum as 132.4 ± 2.4 eV at 5.9 keV, which is very close to the 121-eV limit of CCD236.
... Although dualslope ADCs achieve high resolution, the resolution is linearly proportional to their conversion time, making them relatively slow [22]. High oversampling rate, noise-shaping, delta sigma ADCs can provide high resolution in a shorter time [23,25]. For low frequency operations, SD ADCs are generally used in incremental mode, in which they are first reset and then operated for a fixed number of cycles. ...
... Using higher order modulators or multibit quantizers results in faster response. However, this architecture can only achieve moderate energy efficiency and presents a large area overhead [23][24][25][26]. Compact SD ADCs play important role for some BIST applications [6,7,10,27,31]. ...
... Passive elements synthesis starts with noise optimization. As the comparator noise is extracted through simulations, the remaining noise budget can be calculated using Equations (14) through (23), where flicker noise can be neglected as previously explained. The tool calculates the required C r1 and C r2 values to meet the SNR requirements. ...
We propose a fully differential, synthesizable zoom-ADC architecture with a passive loop filter for low-frequency Built-In Self-Test (BIST) applications, along with a synthesis tool that can target various design specifications. We present the detailed ADC architecture and a step-by-step process for designing the zoom-ADC. The design flow does not rely on the extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in the 65nm CMOS process. The first ADC achieves a 90.4dB Signal-to-Noise Ratio (SNR) in 512μs measurement time and consumes 17μW power. The second design achieves a 78.2dB SNR in 31.25μs measurement time and consumes 63μW power.
... Instead of a continuous-time ADC, a switched-capacitor topology was chosen to take advantage of its good accuracy and linearity. To increase the input signal swing while relaxing the slewing requirements of the integrators, a cascade of integrators feedforward (CIFF) topology [26] was chosen ( Fig. 4.a). By setting the sampling frequency to 750 kHz and the signal bandwidth to 5.8 kHz, an oversampling ratio of 64 was achieved, which is sufficiently high to guarantee a resolution of 16 bits with a time resolution of 0.17 ms, if proper filtering is used [7]. ...
A monolithic multi-functional CMOS microelectrode array system was developed that enables label-free electrochemical impedance spectroscopy of cells in vitro at high spatiotemporal resolution. The electrode array includes 59,760 platinum microelectrodes, densely packed within a 4.5 mm × 2.5 mm sensing region at a pitch of 13.5 μm. A total of 32 on-chip lock-in amplifiers can be used to measure the impedance of any arbitrarily chosen subset of electrodes in the array. A sinusoidal voltage, generated by an on-chip waveform generator with a frequency range from 1 Hz to 1 MHz, was applied to the reference electrode. The sensing currents through the selected recording electrodes were amplified, demodulated, filtered, and digitized to obtain the magnitude and phase information of the respective impedances. The circuitry consumes only 412 μW at 3.3 V supply voltage and occupies only 0.1 mm
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, for each channel. The system also included 2048 extracellular action-potential recording channels on the same chip. Proof of concept measurements of electrical impedance imaging and electrophysiology recording of cardiac cells and brain slices are demonstrated in this paper. Optical and impedance images showed a strong correlation.
... 2) Delta-Sigma ADC: The block diagram of the ΔΣ-ADC is shown in Fig. 16. It uses a third-order cascaded integrators with feedforward modulator structure [36]. It operates for a predetermined number of clock periods and then resets itself. ...
A CMOS terahertz (THz) detector implemented in a 180-nm standard CMOS process is proposed, and room-temperature detection of 0.94-THz radiation is demonstrated. The detector consists of an integrated on-chip patch antenna and a source-feeding NMOS transistor as the rectifying element. To improve the power transfer efficiency between the patch antenna and NMOS transistor, a novel short-stub matching network is proposed. An open quarter-wavelength microstrip transmission line connecting gate is proposed to eliminate the influence of the bonding wire and pad on the antenna-transistor impedance matching. Illuminated by a 0.94-THz BWO source, the measured voltage responsivity (Rv) and noise equivalent power (NEP) of the detector are 31 V/W and 1.1 nW/Hz1/2, respectively.
