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This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching t...
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... are made of a predriver and an output stage. To generate the output voltage swing, the driver needs to supply a load current . Further- more, both the predriver and the output stage consume current. Equation (2) describes the current breakdown in the driver (2) II. TRANSMIT DRIVER TOPOLOGIES LVDS drivers are either current or voltage mode. Fig. 3 shows the simplified models of current-and voltage-mode topologies for a transmit driver. In general, current-mode drivers consume more power but offer better reflection perfor- mance. This is due to the fact that current sources have high output impedances that have minimal impact on the chip output termination impedance. In the case ...
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Citations
... [2,5] . ...
A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.
... As in most point-to-point data communication systems, an LVDS data transfer system consists of a transmitter, a receiver, and a transmission media. Per the standard, the transmitter's output signal should have a common-mode voltage between 1.125 and 1.375 V, and an amplitude swing between 250 and 450 mV [1][2][3][4][5]. These relatively low voltage swing requirements enable LVDS to consume less power compared to other signaling standards. ...
... These relatively low voltage swing requirements enable LVDS to consume less power compared to other signaling standards. Since data is sent differentially, the LVDS standard combines the ability to deliver high data rates while consuming low power with high noise immunity and low electromagnetic interference (EMI) [3][4][5]. Further, the standard increases the interface's tolerance to ...
... ground mismatch between the transmitter and the receiver [4,5]. Therefore, these properties enable LVDS based ICs to deliver data in high frequencies while offering acceptable signal-to-noise ratios. ...
This paper presents a novel design topology of a 5 Gbps PMOS-based low voltage differential signaling (LVDS) voltage mode output driver. The topology is designed to meet the requirements of low power consumption and high data rates applications. The driver consists of an output stage and a pre-driver stage where the driver’s swing and common-mode output voltage are set. The pre-driver and the output stage consume only 13.1 mW of power at 5 Gbps speed while operating from a 1.8 V voltage supply. Further, the design achieved −21 dB return loss performance at DC. The driver was extracted and simulated using Mentor Graphics CAD tools and implemented in 180 nm CMOS technology. The output signal is fully compliant with the LVDS standard output swing and common-mode voltage specifications.
... The circuit consists of a linear equalizer and an output stage. The output stage can achieve good line impedance matching while keeping the power consumption very low using a positive feedback technique [13]. Pre-emphasis capability is achieved in the linear equalizer by introducing a high frequency boost. ...
... As a result, the output stage power consumption is dominated by the load current. This is a major power saving advantage over CML based topologies where the tail currents are four times the load current [13]. ...
This paper describes a 12.5 Gbps voltage mode transmitter with a high speed signal conditioning capability. Using a linear equalizer that is followed by a power efficient output stage, the transmitter achieves pre-emphasis at very low power consumption. In measurements, the transmitter can reliably transmit a 12.5 Gbps PRBS7 signal through a lossy 14 in. FR4 stripline commonly used in backplanes. It achieves a peak to peak jitter of 24 ps, a differential eye opening amplitude of 120 mV, and a maximum common mode ripple of 40 mV. The proposed topology consumes 33 mW at-speed power which includes both the output stage and the linear equalizer. It also passes 8KV HBM ESD testing without compromising the high speed capability. The transmitter is fabricated in a 130 nm BiCMOS technology with 100 GHz maximum ft and packaged in a commercial leadless leadframe package.
... Transmit drivers are often categorized into current mode drivers or voltage mode drivers [4]. Figure 1 illustrates the basic schematic of each driver. ...
... In general, current mode drivers consume more power but have better signal reflection performance, because an internal linear resistor is used to match the line impedance. On the other hand, voltage mode drivers consume less power, but the system suffers from nonlinear impedance behavior during signal switching which may affect the signal integrity [4]. For an LVDS system to operate, a signal and its compliment are fed into the input pins of the drivers shown in figure 1. ...
... Since Q5 and Q6 are in saturation, their output resistance is high and should not affect the circuit. (3) Equation 4 shows that the pre-driver current is a fraction of the load current. Therefore, by making R PRE large, the system can be designed to consume very low power at the pre-driver stage compared to other driver topologies. ...
This paper presents a new topology of a PMOS based LVDS voltage-mode output driver. This topology is designed to meet the requirements of low power consumption and high data rates applications. The driver, which consists of a pre-driver stage and an output stage, uses a positive feedback technique at the output stage to achieve line impedance matching and power saving. The pre-driver stage is used to set the driver's swing and common mode output voltage. The pre-driver and the output stage consume only 9mW of power at 3 Gbps speed while operating from a 1.8V voltage supply. The system is designed and simulated using CMOS 180nm technology and is fully compliant with LVDS output swing and common mode voltage specifications.
... Topologically, the current mode driver is similar to LVDS (Low voltage differential signaling) [5] [11]. Being differential in nature, it has excellent noise immunity & reduced amount of noise immusion. ...
... Step response of the link for 7.5 inch, & 18.5 inch International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012NMOS transistors receiving 1 bit are ON. So the polarity of current will be negative as the current is sinked from top branch of transmission line. ...
The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.
... Topologically, the current mode driver is similar to LVDS (Low voltage differential signaling) [5] [11]. Being differential in nature, it has excellent noise immunity & reduced amount of noise immusion. ...
... Step response of the link for 7.5 inch, & 18.5 inch International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012NMOS transistors receiving 1 bit are ON. So the polarity of current will be negative as the current is sinked from top branch of transmission line. ...
The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive un terminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed off chip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.
... In many SerDes circuits, current mode logic (CML) drivers have been applied [2][3], whereas they have drawbacks such as the static power dissipation and the limit to provide a large range of termination voltages. Source-seriesterminated (SST) drivers can overcome these disadvantages [4], which only consume ¼ output stage power of CML drivers and support high-swing termination voltage. As well as attaining low power operation, maintaining signal integrity is another key point in SerDes circuit design. ...
A low power source-synchronous source-series- terminated (SST) transmitter (Tx) in 65 nm CMOS technology is presented. The Tx, comprised of nine data/control channels, a forwarded-clock channel and one PLL, merely dissipates 26.2 mW/channel while exhibiting a 750 mV differential eye height at 6.4 Gbps. The SST drivers can save ¾ output stage power of CML ones, and moreover, the proposed novel topology can independently control impedance self-calibration and equalization. To implement half-rate architecture, the PVT- tolerant PLL provides a pair of quadrature clocks with 2.5 ps rms cycle to cycle jitters running at 3.2 GHz.
To enhance sampling rates of CMOS digital-to-analog converters (DACs), analog multiplexing of several DAC output signals in the time domain provides a solution. In this article, a full CMOS integration of two sub-DACs and an active analog multiplexer (AMUX) on a single chip in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology is presented for the first time for sampling rates of 100 GS/s and beyond. Sampling rates up to 108 GS/s for broadband pulse-amplitude modulated (PAM) signals and up to 118 GS/s for oversampled signals are shown outperforming previously reported data in terms of sampling rate or data rate, respectively. Two 8-bit sub-DACs up to 59 GS/s with CMOS inverter-based output drivers and pseudo-segmentation provide the analog input data for the 2:1 AMUX realized in current-mode topology. An additional on-chip memory of 256 kB completes the system to a universal arbitrary waveform generator (AWG). At 100 GS/s, the total power consumption is about 4 W. Generally, an AMUX is able to shift the limits of DACs in well-established CMOS technologies toward higher frequencies independent on technology advances and opens a second, conceptual path for achieving higher sampling rates with an additional benefit of a principle bandwidth extension by the AMUX operation.
This paper presents the design and the test results of a low-power 5 Gbps 10:1 serializer chip with the self-check function based on a standard 130 nm CMOS technology. This serializer chip adopts a multi-level design scheme with a combination of the multi-phase structure (5:1 module) in the low data rate part and the tree structure (2:1 module) in the high date rate part. The high data rate 2:1 module adopts a latch-induced latency control circuit to ensure the timing margin across corners. The serializer chip has been fully tested, wide-open 5 Gbps output eye diagram has been captured, and the logic function has also been verified. The measured power consumption of the whole chip is 42 mW including Rx/Tx, and the power consumption of the serializer core is around 12.1 mW.
