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Source publication
A U-interface line driver for a single-chip ISDN (integrated
services digital network) NT (network termination) in an advanced 3.3-V,
0.5-μm CMOS technology is presented. It features a THD (total
harmonic distortion) better than -68 dB for an output swing of 5
V<sub>pp</sub> on a 67-Ω load in a band up to 60 kHz. A novel
quiescent current control c...
Contexts in source publication
Context 1
... a standard pseudodifferential circuit with push-pull class- drivers [2]- [5]. This circuit is easier to design than a fully differential driver since it requires no common mode feedback (CMFB). Each driver is configured as an inverting amplifier with gain with respect to the analog ground. A simplified block diagram of the line driver is shown in Fig. 2. In this figure, one of the driver stages is further detailed, showing the single-ended, high-gain first stage, followed by two lower gain error amplifiers, which drive the large PMOS and NMOS output transistors in the output ...
Context 2
... straightforward pole splitting over the error amplifiers has been used for the stabilization of the driver (Fig. 2). This simple pole splitting was only possible due to the limited GBW of the driver and the high gain in the error amplifiers. As explained above, the GBW could be limited by the proper choice of the quiescent current and transistor sizes, while the high gain in the error amplifiers is the result of the new quiescent current control ...
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Citations
In this chapter the last interfacing block to the line, being the line driver is addressed. The use of multi-tone modulation schemes in recent telecommunication systems raise the power consumption of these building blocks enormously, creating a new bottleneck. Soon, the classical class AB solutions will be no longer applicable from a power efficiency point-of-view. More advanced circuit techniques like class G and class H are emerging. Ultimately switching type amplifiers, which suffer the high bandwidth and linearity constraints, will have to be used to decrease the power dissipation.
An AQC class-AB amplifier has been designed with low THD and
quiescent power consumption. It uses the 0.8 μm 10 V BiCMOS process,
and occupies 1.8 × 1.6 mm. It has <0.3 %, THD+N over the audio
frequency range driving 1 W into 8 Ω. It consumes 2.6 mA at
quiescent condition and has 65.1 % power efficiency
In this paper, we designed 3.3-V line drivers for DSL (digital subscriber line) applications. The line driver consists of pre-amplifier, error amplifiers, output transistors, and quiescent current (IQ) control circuits. A new method is proposed for the quiescent current control circuit in order to obtain high linearity performance. One driver is designed for ISDN U-interface and the other for HDSL applications. Both drivers are fabricated in a 0.35-μm n-well CMOS technology and THD (total harmonic distortion) better than -64 dB is achieved
The internet revolution has led to the demand for high speed, low cost solutions for providing high bandwidth to the consumers. Cable and DSL systems address these requirements through sophisticated analog and digital signal processing schemes. A key element of the analog front end of such systems is the line driver which interfaces with the transmission medium such as co-axial cable or twisted pair. The line driver is an amplifier that provides the necessary output current to drive the low impedance of the line. The main requirements for design are high output swing, high linearity, matched impedance to the line and power efficiency. These requirements are addressed by a class AB amplifier whose output impedance can be controlled through feedback. The property of this topology is that when the gain is unity, the output resistance of the driver is matched to the line resistance. Unity gain is achieved for varying line conditions through a tuning loop consisting of peak-to-peak detectors and differential difference amplifier. The design is fabricated in 0.5 micron AMI CMOS process technology. For line variations from 65 to 170 ohms, the gain is unity with an error of 3 % and the impedance matching error is 20 % at the worst-case. The linearity is better than 50 dB for a 1.2 V peak-to-peak signal over the signal bandwidth from 10 kHz to 5 MHz and the line resitance range from 65 to 160 ohms.
Matching I/O driver output resistance to transmission line impedance is critical for high speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage and temperature variations, that same calibration circuitry may perform improperly. This paper presents an I/O driver design that is less sensitive to process, voltage and temperature variations. The proposed driver design provides a near linear, or flat, output resistance response verses output voltageMatching I/O driver output resistance to transmission line impedance is critical for high speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage and temperature variations, that same calibration circuitry may perform improperly. This paper presents an I/O driver design that is less sensitive to process, voltage and temperature variations. The proposed driver design provides a near linear, or flat, output resistance response verses output voltage.
A central office ADSL-VDSL line driver in a 0.35 μm 3.3 V CMOS technology is presented. The chip has a missing tone power ratio (MTPR) over 55 dB driving ADSL signals and can deliver VDSL downstream signals with a bandwidth of 8.6 MHz and an out-of-band PSD of -103 dBm/Hz. The power efficiency is 47% for 100 mW ADSL signals with a crest factor of >5.
System optimization of the Analog Front End (AFE) and hybrid line interface is a key contributor in achieving high data rate and long reach for Asymmetric Digital Subscriber Line (ADSL) modems. Following a brief review of the ADSL system, the basic building blocks in an AFE, analog line interface, and hybrid matching issues are introduced. Integration trends of a single-channel AFE and circuit design challenges for multi-channel AFE are then presented. Line driver technologies and line receiver design issues are discussed with emphasis on the tradeoff between noise and linearity. Finally, design challenges for a highly integrated ADSL modem chipset with minimal external components are addressed.
An analog line driver for video applications is presented. Utilizing a class AB error amplifier structure, the design achieved 1.2 V peak to peak output swing with better than 45 dB linearity for frequencies up to 5 MHz. An adaptive tuning scheme for output impedance matching using peak detection is used to provide uniform performance across line impedance variations. The circuit is designed in AMI 0.5μm CMOS technology and has a tuning range of 65 to 135 ohms with a power consumption of about 34 mW.
A 5V 0.5μm CMOS line driver has distortion <-65dB in the
ADSL upstream band for a 4V peak-to-peak differential output swing on a
12.5Ω load. The quiescent current is controlled digitally with a
dedicated algorithm that corrects for offsets and process variations.
The driver is integrated in a complete ADSL CPE analog front-end
A fully integrated CMOS line driver for use in High Bit-Rate Digital Subscriber Line (HDSL) services is presented. The circuit is fabricated in a single-poly quad-metal 0.35 μm process and features ⩽70 dB THD while driving up to ±2.4 V, 200 kHz signals into 30 Ω with a 3 V supply. The circuit is configured as a gain of 6.0 non-inverting amplifier and as such has negligible input resistance and minimal input capacitance (<200 fF). The circuit dissipates less than 60 mW of quiescent power with a 3 V supply and is functional with supply voltages as low as 1.5 V
