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The paper presents a simple true random number generator (TRNG) which can be embedded in digital Application Specific Integrated Circuits (ASICs) and Field Programmable Logic Devices (FPLDs). As a source of randomness, it uses on-chip noise generated in the internal analog phase- locked loop (PLL) circuitry. In contrast with traditionally used free...
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... digital VLSI circuits use advanced clock generation and distribution circuitry based on embedded analog PLLs [7], [8], [9], [10]. A simplified block diagram of one analog based PLL block available in advanced digital circuits is depicted in Figure 1. Each PLL block can provide at least one synthesized clock signal with frequency OUT F : ...
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Citations
... There are various HTRNG designs, such as the classical ring oscillator TRNG based on phase jitters [SMS07], PLL-based TRNG [DSFC04] and transient effect ring oscillator (TERO) TRNG [VD10]. In 2006, Jovan Dj. ...
TRNG is an essential component for security applications. A vulnerable TRNG could be exploited to facilitate potential attacks or be related to a reduced key space, and eventually results in a compromised cryptographic system. A digital FIRO-/GARO-based TRNG with high throughput and high entropy rate was introduced by Jovan Dj. Golic (TC’06). However, the fact that periodic oscillation is a main failure of FIRO-/GARO-based TRNGs is noticed in the paper (Markus Dichtl, ePrint’15). We verify this problem and estimate the consequential entropy loss using Lyapunov exponents and the test suite of the NIST SP 800-90B standard. To address the problem of periodic oscillations, we propose several implementation guidelines based on a gate-level model, a design methodology to build a reliable GARO-based TRNG, and an online test to improve the robustness of FIRO-/GARO-based TRNGs. The gate-level implementation guidelines illustrate the causes of periodic oscillations, which are verified by actual implementation and bifurcation diagram. Based on the design methodology, a suitable feedback polynomial can be selected by evaluating the feedback polynomials. The analysis and understanding of periodic oscillation and FIRO-/GARO-based TRNGs are deepened by delay adjustment. A TRNG with the selected feedback polynomial may occasionally enter periodic oscillations, due to active attacks and the delay inconstancy of implementations. This inconstancy might be caused by self-heating, temperature and voltage fluctuation, and the process variation among different silicon chips. Thus, an online test module, as one indispensable component of TRNGs, is proposed to detect periodic oscillations. The detected periodic oscillation can be eliminated by adjusting feedback polynomial or delays to improve the robustness. The online test module is composed of a lightweight and responsive detector with a high detection rate, outperforming the existing detector design and statistical tests. The areas, power consumptions and frequencies are evaluated based on the ASIC implementations of a GARO, the sampling circuit and the online test module. The gate-level implementation guidelines promote the future establishment of the stochastic model of FIRO-/GARO-based TRNGs with a deeper understanding.
... Rasgele sayıların tamamının güvenilir bir kaynaktan sağlanması amacıyla kriptolojide GRSÜ' leri diğer yöntemlere nazaran daha çok kullanılmaktadırlar[99][100]. Çünkü bu yapılar entropi kaynağı olarak deterministik karaktere sahip olmayan doğal fiziksel olayları kullanmaktadır. ...
The random number generators are used in many areas such as cryptography, the applications where the
Monte-Carlo method is used, the application of numerical analysis with computer simulations and modeling.
TRNGs that is used in the field of cryptography and secure communications require fast, secure and intensive
process of the physical methods that do not have deterministic character are used as entropy source. These
methods are direct reinforcement, dual oscillator and chaos-based applications. In recent years the great
efforts are being made in the area of developing the chaos-based TRNG structures due to noise-like features
and the ability of hiding informatory sign of chaotic oscillators. Chaos based TRNG‘s within the digital
circuits are an effective alternative to the traditional chaos-based analog structure. Because TRNG systems
that use analog chaotic signal generator are difficult to be synchronized with the transmitter and receiver. In
addition, the weak resources that generates physical noises like thermal or scattering are used on the
implementation of these circuits. The digital-based FPGA chips have a significant potential in improving the
information security capabilities in some applications as cryptology and securing the communication which
requires high performance and processor power. In this study, performance differences between conventional
method of TRNG that used chaotic system and recently designed FPGA based chaotic systems have been
compered.
... The PowerPC processor utilizes the Mersenne Twister algorithm to generate pseudorandom numbers. This algorithm was chosen on the basis of comparisons performed in [8,12]. ...
A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was de-veloped to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark prob-lem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.
... • Development and testing of NIOS II based designs extended with custom peripherals [14] embedded into EP2C35 Cyclone FPGA device. Such designs represent the most complex designs based on hardware/software co-design. ...
The paper describes a remotely accessible laboratory system that allows performing experiments remotely from anywhere across the Internet via web interface as well as locally in the classroom. The system is aimed at courses of advanced digital design and signal processing using complex Field Programmable Gate Array (FPGA) platforms. It is a powerful tool that allows students the full access to laboratory equipments and FPGA platforms remotely from any remote terminal with any common web browser and standard remote desktop interface. The system consists of Altera development FPGA kits, suitable instrumentation and a PC running an interactive LabView based software including a Graphical User Interface (GUI). A logic analyzer, a digital storage oscilloscope, and a pattern and arbitrary waveform generators are part of the workplaces to enable testing and debugging of FPGA applications under development.
... • Development and testing of NIOS II based designs extended with custom peripherals [13] embedded into EP2C35 Cyclone FPGA device. Such designs represent the most complex designs based on hardware/software co- design. ...
The paper presents a remote laboratory system that allows performing experiments controlled across the Internet via web interface as well as locally in the classroom. The system has been developed for courses of advanced digital design and signal processing using complex Field Programmable Gate Array (FPGA) platforms. It allows students full access to laboratory equipments, advanced software licenses, and FPGA platforms remotely using any common web browser and standard remote desktop interface. The system consists of Altera development FPGA kits and suitable instrumentations (Logic Analyser, Digital Oscilloscope, and Vector Signal Generator) or low cost alternative (DAQ board as a Virtual Logic Analyser, Oscilloscope and Vector Signal Generator). Both solutions use PC running an interactive LabVIEW based software including a Graphical User Interface (GUI).
... This method is perfectly suited for modern FPGAs with internal analog PLL circuitry. The implemented TRNG provides random data with good quality also for simplified architecture [16] actually used in the proposed SoC. The implemented TRNG is designed for projected R = 40, 000 bit/s (more than a typical SoC can require in expected applications) by proper setting of used PLLs. ...
... where R is the bit-rate of the output TRNG sequence. It has been shown in [11], [16] that if K M and K D are relatively prime, the requirement for TRNG design to work reliably is ...
The paper introduces a cryptographic system on a chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is built on three main blocks - embedded soft-core with industry standard ARM7 architecture, internal Flash and static RAM memory blocks and custom true random number generator (TRNG) design. High flexibility of the SoC is based on efficient software implementation of main cryptographic primitives (AES, ECC, RSA, SHA) in soft-core. Implemented TRNG uses PLL-based simplified architecture with optional on- chip free running RC oscillator.
... metastability [5]). Although these limitations can be overcome by a design of proper custom circuits, randomness extraction is still a big challenge in the designs based on off the shelf devices as FPGA [6], [7] or general microprocessors [8]. ...
This paper presents a new chaos-based True Random Number Generator (TRNG) with decreased voltage supply sensitivity. Contrary to the traditionally used sources of randomness it uses well-defined deterministic switched-capacitor circuit that exhibits chaos. The whole design is embedded into commercially available mixed-signal PSoC reconfigurable device without any external components. Proposed design is optimized for reduction of influence of supply voltage to the quality of generated random bit stream. The influence of circuit non-idealities is significantly reduced by the proposed XOR corrector and optimized circuit topology. The ultimate output bit rate of proposed TRNG is 60 kbit/s and quality of generated bit-streams is confirmed by passing standard FIPS and correlation statistical tests performed in the full range of PSoC device supply voltages.
... To reduce the subjectivity of the board design strategy, we have selected the Altera DSP Development board with a Stratix EP1S25F780C5 device [8] for jitter measurements and TRNG implementation. The jitter has been measured similarly in [9] using Agilent Infiniium DCA 86100B wide bandwidth oscilloscope. We have found that in comparison to the Nios board with APEX [10] (used as a reference in [4]) the jitter is significantly smaller. ...
... In [4] we used delay elements to increase the probability of overlapping of CLK and CLJ edge zones. In [9] we showed that the delay line is not needed for known values of jitter, when σ jit MAX(∆T min ). The decimated output signal (6) which is generated at the output of an Exclusive-OR (XOR)-based decimator [11] as a bit-wise addition modulo 2 (⊕) of samples q(.) sampled with the frequency F CLK , will be nondeterministic, too. ...
... Since the TRNG requires at least MAX(∆T min ) ≈ σ jit (9) or better MAX(∆T min ) σ jit (10) then the first practical design condition is (see equation 4): ...
The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic
Devices (FPLDs). As a source of randomness, an on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry
is used. In contrast with traditionally used free running oscillators, it uses and extends a recently developed method of
randomness extraction based on two rationally related clock signals. Although it was developed for the Stratix family, the
principle can be easily employed in other digital devices containing analog PLLs. We use the large flexibility of PLLs embedded
in Stratix family to demonstrate the relationship between PLL and TRNG configuration, the quality of output random bit-stream,
and the speed of the generator. The quality of TRNG output is confirmed by applying statistical tests, which pass also for
a high-speed version of the generator giving up to 1M random bits per second. The generator developed for cryptographic applications
helps to increase the system security, but it can also be used in a wide range of other applications.
This paper presents a new type of True Random Number Generator (TRNG) based on jitter and metastability implemented in the latest family of Xilinx FPGA devices. The source of randomness is the Phase-Locked Loop (PLL) that is present on such devices, which exhibits jitter due to one of the analog component in it. For extracting the random bits the design uses the same clock as the PLL's input clock. The quality of the TRNG is given by the entropy source used, the single-chip implementation, and the high throughput (of the order of several megabits per second) obtained. It is confirmed by the fact that all the classical test batteries (NIST, DIEHARD, Test U01 and ENT) yielded very good results when ran on the generated random bits stream.
