Simplified FPGA Block Diagram (Courtesy Xilinx, Inc) 

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... Aerospace Engineering at the University of Colorado – Boulder. He completed the Ph.D. degree in Electrical Engineering at Ohio University conducting his graduate research within the Avionics Engineering Center. His research interests include GPS/CDMA receiver architectures, RF design, and software radios. Todd Walter is a Senior Research Engineer in the Department of Aeronautics and Astronautics at Stanford University. Dr. Walter received his Ph.D. from Stanford University in 1993. His current research interests are developing WAAS integrity algorithms and analyzing the availability of the WAAS signal. He is a Fellow of the ION. Per Enge is a Professor of Aeronautics and Astronautics at Stanford University, where he is the Kleiner-Perkins, Mayfield, Sequoia Capital Professor in the School of Engineering. He is also the Director of the GPS Research Laboratory, which works with the Federal Aviation Administration, U.S. Navy and U.S. Air Force to pioneer systems that augment the Global Positioning System (GPS). Prof. Enge has received the Kepler, Thurlow and Burka Awards from the Institute of Navigation for his work. He is a Member of the National Academy of Engineers (NAE), a Fellow of the ION, and a Fellow of the IEEE. Over the next decade, civilian users will have access to multiple GNSS signal frequencies and constellations. This drastic increase in signals and their frequencies creates substantial opportunities and requirements for analysis and validation. Such analysis and validation is of significant importance from an aviation integrity perspective. The ultimate goal of our research efforts is to develop a standalone reconfigurable platform capable of tracking and monitoring multiple constellations and frequencies as and when they commence transmission. This platform will also be utilized to test and verify new receiver processing algorithms currently under development. It must be capable of running in real-time to ensure signals can be monitored on a 24x7 basis. As a first step in this direction, we designed and validated a standalone L1 C/A receiver which runs in real-time on a Xilinx University Program Virtex-II Pro Development Board. This board features a Virtex-II Pro FPGA with two on-chip PowerPC 405 32-bit RISC hardcore processors. This feature of the FPGA fabric facilitates the development of reconfigurable embedded GNSS receivers which do not require the resources of a Host PC or a dedicated DSP processor. The entire system was designed using the Xilinx System Generator for DSP, a modeling and implementation tool for high-performance DSP systems. Such a model-based design approach facilitates rapid system development and prototyping thereby enabling system modifications and upgrades to be implemented in a short time span. Present day GNSS civilian users have unrestricted access to only the GPS L1 C/A and Glonass Standard Precision (SP) ranging signals. Over the course of the next decade, users will be able to access multiple frequencies and constellations. In addition to new signals on GPS, GNSS constellations such as the European Union’s Galileo and China’s Compass along with a modernized Russian Glonass system will provide multiple ranging sources to GNSS users. Some of the proposed frequencies and constellations are shown in Figure 1. Most of these systems will be interoperable since they will be modulated by a common set of carrier frequencies. The possibility of obtaining dual-frequency measurements will help improve accuracy for civilian users while enhancing system integrity, availability, and continuity for aviation users. A few of the proposed new GNSS frequencies and constellations currently transmit test signals which may not necessarily be their final signal specifications [1, 2, 3]. SRAM-based Field Programmable Gate Arrays (FPGA) based receivers can be easily reprogrammed making them an ideal choice to acquire, track, and validate new signals whose specifications may not have been finalized. Ease of reprogramming the device makes it an ideal choice for rapid prototyping. FPGAs help overcome the limitations of Application Specific Integrated Circuits (ASICs) and pure software defined radios. While ASICs are optimized for computational efficiency, they cannot be reconfigured to incorporate changes in the Signal in Space (SIS) specifications of the signals for which they are specifically designed for. Software defined radios provide flexibility in incorporating system changes but are computationally expensive. A FPGA device is an integrated circuit with a central array of logic blocks that can be connected through a user configurable interconnect routing matrix. The periphery of logic-array is comprised of a ring of I/O blocks that can be configured to support different interface standards. This flexible architecture can be exploited to implement a wide range of synchronous and combinational digital logic functions. A simplified representation of a FPGA block diagram is shown in Figure 2. A digital design can utilize one or more of three basic types of devices: Logic, Memory and Processors. Several of the current high-end FPGA families incorporate all three of these devices within a single integrated circuit (IC). The ability to implement hardcore or softcore processors within the FPGA makes them well suited for developing reconfigurable embedded systems. Further details about hardcore and softcore embedded processors are provided in a subsequent section of this paper. These FPGA families feature millions of equivalent gates of functionality and high-speed interfaces capable of supporting a broad range of engineering solutions including nontraditional applications. Today, FPGAs are capable of implementing complex functionality such as the correlation process in a GNSS receiver which traditionally is performed on a dedicated ASIC. Apart from the basic three digital components mentioned in the previous paragraph, many newer generation FPGA families also feature dedicated components specifically designed to perform DSP functions. These components accelerate algorithms and enable higher levels of DSP integration and lower power consumption within the device. These dedicated DSP components support over 40 dynamically controlled operating modes including: multiplier, multiplier-accumulator, multiplier- adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, wide counters, and comparators. They also incorporate efficient adder-chain architectures for implementing high-performance filters and complex mathematical operations efficiently. Some FPGA manufacturers also provide users with Intellectual Property (IP) blocks which help implementation of popular DSP algorithms and functions in an optimal manner. Of particular importance for software GNSS receiver development include Math Functions such as the COordinated Rotation DIgital Computer (CORDIC) algorithm used to compute trigonometric functions and specialized DSP algorithms/designs such as the Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filter design. [4, 5] In this paper, we present some preliminary results of our current efforts in developing a reconfigurable embedded GNSS receiver platform capable of tracking multiple frequencies and constellations. This platform will be used for a variety of applications which are discussed in a subsequent section of this paper. As a first step, we designed a real-time reconfigurable embedded GPS L1 receiver and analyzed its performance. We now describe the details of the receiver design and implementation process and compare its performance to that of a pure software defined receiver executed on a Host PC. GNSS software radio receivers have evolved notably over the past few years. It was originally developed in 1997 as a tool for post processing of collected GPS data. Its implementation in Matlab made it computationally expensive [8]. In order to reduce computational expense, pure software receivers were implemented in a high level language such as C/C++ running on a programmable microprocessor. Over the years, through the use of novel processing techniques combined with technology improvements in microprocessor capabilities have enabled implementation of multi-channel real-time GPS L1 C/A software receiver [9, 10]. Such receivers utilize the processing resources of the microprocessor of a host PC and their performance is directly related to the resources available on the host PC. To overcome the computational limitations placed by resource availability on a host PC, various implementations have been proposed which utilize the signal processing capabilities of a dedicated Digital Signal Processing Chip (DSP) and/or the reconfigurable parallel processing capabilities of a FPGA [11, 12, 13] to develop real-time GNSS software receivers. These implementations were designed using hardware descriptive languages (HDL) such as Verilog or Very- High-Speed Integrated Circuits HDL (VHDL) and were executed on hardware platforms custom designed by the authors. Our desire to use a ubiquitous commercial off the shelf FPGA development board influenced the choice of the hardware platform selected for our current work. After comparing the cost and processing capabilities of several development boards, we decided to adopt the Xilinx University Program Virtex-II Pro Development System. In fact, this board is used by over 2000 universities the world over for digital design courses. We are of the opinion that this board can also be utilized as an attractive educational tool for GNSS software receiver design courses. The development board is distributed by Xilinx Inc., through its Xilinx University Program (XUP) to universities affiliated with the program. It features a Virtex II-Pro FPGA chip along with onboard external memory modules, I/O ports and other peripherals. By using this particular development board, we could avoid the time and costs associated with designing a custom ...