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Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study memory that can perform computation as well as store data within a generic memory array in a non-Vo...
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Context 1
... case of write operation, Write Recovery phase may follow the Restore phase. Referring to the relative timing of Figure 6, adding a column write command just means that a precharge command is issuable only after data restoration process is complete correctly. The time required for write data to overwrite the sense amplifier and update the cell is named as the write recovery time t WR in Figure 5. ...
Context 2
... are performed for the memory read cycle at the normal operating voltage of 1.2 V in a 90 nm logic-compatible CMOS process. Figure 6 presents the voltage waveforms of the bitlines and selected control signals in one sense amplifier implemented as arrays in this work. Note that before a row access operation gets started, RBL (and RBLB not shown in the figure) is precharged and the voltage on RBL is set to V REF . ...
Context 3
... the asserted SAN and SAP quickly drive RBL to reach a full voltage level V DD and finally restore charge onto the cell capacitor. Figure 6 also shows the relationship among timing parameters of interest for a read command. After the delay t RCD from the initiation of row access operation, sensing and amplification are performed and the data is available and ready to be read from the sense amplifiers onto the device data bus through the column access process. ...
Citations
... The WWL decoder signal is boosted to V BOOST using the global level shifter. Prior eDRAMs [36][37][38][39] had popularly employed an inverter-based sense amplifier to detect the voltage of RBL during the read operation because of its compact implementation. However, the inverter-based sense amplifiers were prone to parasitic capacitance, resistance of the RBL, and leakage current by inactivated gain cells. ...
... At this time, a sense-amplifier enable (SAE) signal is activated, and the differential sense amplifier compares voltage of the discharged RBL with a reference voltage VREF. Prior eDRAMs [36][37][38][39] had popularly employed an inverter-based sense amplifier to detect the voltage of RBL during the read operation because of its compact implementation. However, the inverter-based sense amplifiers were prone to parasitic capacitance, resistance of the RBL, and leakage current by inactivated gain cells. ...
This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM’s retention time. The implementation of a homogeneous NMOS-based 2T gain cell not only reduces write access times but also benefits from a boosted write wordline technique. In a comparison with the previous pseudo-static gain cell design, the proposed PS-nGC exhibits improvements in write and read access times, achieving 3.27 times and 1.81 times reductions in write access time and read access time, respectively. Furthermore, the PS-nGC demonstrates versatility by accommodating a wide supply voltage range, spanning from 0.7 to 1.2 V, while maintaining an operating frequency of 667 MHz. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the prototype features an efficient active area, occupying a mere 0.284 µm2 per bitcell for the 4 kb eDRAM macro. Under various operational conditions, including different processes, voltages, and temperatures, the proposed PS-nGC of eDRAM consistently provides speedy and reliable read and write operations.
... To overcome these limitations, PIMs with embedded dynamic random-access memory (eDRAM) have been proposed [11][12][13]. Logic-compatible eDRAMs [14][15][16][17] can offer a higher bit density and smaller area than those of the SRAMs. Hence, the eDRAM-based PIM can realize more area-efficient implementation than that of the SRAM-based PIM. ...
... To overcome these limitations, PIMs with embedded dynamic random-acc memory (eDRAM) have been proposed [11][12][13]. Logic-compatible eDRAMs [14][15][16][17] c offer a higher bit density and smaller area than those of the SRAMs. Hence, the eDRA based PIM can realize more area-efficient implementation than that of the SRAM-bas PIM. ...
This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.
The operation of a low-temperature solar thermal system using artificial neural networks (ANNs) models of its components (flat-plate solar collector, internal heat exchanger, and stratified tank), and its working with dynamic and static modes, has been simulated. The ANNs models of these components, used as blocks, have been previously formulated using the experimental data of solar irradiance, ambient temperature, flow and temperature of the working fluid and water supplied to the tank, and stratification temperatures in eight levels of the tank, measured under the continental Mediterranean climate conditions of the center of the Iberian Peninsula. The simulation, executed in intervals of 1 min, was run for two individual days and each month of 1 year. The f-Chart method was used to validate the neural simulation under the same conditions (without stratification) for 10 years, resulting in an average deviation of the performance of 1.85%. The results for 1 day at stratification temperatures show a root-mean-square error (RMSE) value of 0.77°C in dynamic operation mode and 0.13°C in static operation mode.
