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![Fig. 3. Conceptual Common-Mode Feedback block [17].](profile/Arthur-Oliveira-7/publication/309772779/figure/fig3/AS:426488425127939@1478694172447/Conceptual-Common-Mode-Feedback-block-17_Q320.jpg)
Fully Differential amplifiers play a critical role in systems which differential signaling is present. One drawback of designing this kind of circuit is the need of an extra circuit to keep it stable. This paper presents a methodology for automatic design of fully differential amplifiers with output balance considering both main-amplifier and commo...
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... A multiple feedback filter topology was chosen as the first case study circuit. It was implemented with the Fully Differential Amplifier (FDA) presented in [22] in a 180 nm CMOS process. The values of capacitances and resistances of passive components were designed in order to implement a low pass Butterworth filter with the cutoff frequency of 10 kHz. ...
... The sizing of the transistors are shown in Table 1. The W/L dimensions were defined in [22] by an automatic design optimization tool presented in that work. ...
This work presents a low cost automatic test generation tool for structural analog testing. With the spice netlist and technology models of the circuit to be tested, a fault list is generated, considering a defect modeling provided by the user. The tool interacts with a spice simulator, simulating the fault-free and faulty circuits. The test development considers DC, AC (single tone) and transient (step) stimuli applied at the primary circuit inputs, computing the obtained fault coverage when taking different circuit nodes as observation points. The final test set determination relies on a fault dictionary that helps maximizing the fault coverage, at the same time as minimizing the test application. Since different circuit nodes are observed during the fault simulation campaign, this tool also helps the test developers and designers on defining Design-for-Testability strategies to increase fault detection by covering the undetected faults identified. The feasibility of the proposed method and the applicability of the tool are demonstrated with two case-studies, consisting in fully-differential integrated filters designed on a commercial 180 nm process. Results show that fault coverages near to 95% are obtained in both case-studies while requiring small test sequences with simple parametric measurements.
... A multiple feedback filter topology was chosen as a case study circuit. It was implemented with the Fully Differential Amplifier (FDA) presented in [16] in a 180 nm CMOS process. The values of capacitances and resistances of passive components were designed in order to implement a low pass Butterworth filter with the cutoff frequency of 10 kHz. ...
... This work uses a simulation-based automatic synthesis tool called UCAF [5]. This tool was developed in our research group and was already used in previous works for the automatic design of fully differential amplifiers [6]. This tool uses an optimization heuristic, that can be either Simulated Annealing or Genetic Algorithms, to explore the design space for finding optimized solutions. ...
... The required inputs to start the amplifier design are the specifications of the circuit that will be constraints in the optimizations process, the technology data in which the circuit will be designed and the algorithm configuration. As presented in [6], the first stage is designed using an ideal model of the CMFB circuit. With the specifications matching the constraints, the CMFB is replaced by the real circuit, and then this circuit is sized through the optimization tool in order to maintain the same performance obtained using the ideal CMFB model. ...
This paper presents an optimized-based design methodology for the automatic design of two-stage fully differential amplifiers. The design of two-stage fully differential amplifiers lies in the need of extra circuits such as the common-mode feedback (CMFB) and the second pole compensation circuitry. In order to validate the methodology, a two-stage fully differential amplifier was designed in 0.13 µm CMOS technology with a 1.2 V power supply. This amplifier is composed by a folded-cascode amplifier in the first stage and two common source (CS) amplifiers as the second stage. The second pole compensation is done using a no capacitor feed-forward (NCFF) technique. The results presented in this paper are obtained without considering the zero-pole pair mismatch due to the employed NCFF technique.
... Fully differential amplifiers are largely used in mixedsignal integrated circuits because this type of circuit presents several advantages, if compared to single-ended amplifiers, such as increased immunity to external noise, increased output voltage swing for a given voltage rail and reduced even-order harmonics [10]. However, FDAs usually need an extra block, known as common-mode feedback (CMFB) circuit, to guarantee the correct functionality of the amplifier [11]. The CMFB circuit is responsible to provide stable levels of output common mode voltage for all range of operating frequencies of amplifier [12]. ...
... The circuit studied in this work consists of a single stage FDA. The amplifier was designed considering the 0.18µm process from X-FAB [11]. Both the amplifier and the CMFB schematics are shown in Figures 2 and 3, respectively. ...
... and 3.07mV, respectively. The transistors sizes of the FDA and CMFB blocks and the bias current Io can be obtained in [11]. ...
This paper presents a simple and low-cost test methodology applied to fully differential amplifiers (FDAs). This kind of amplifier needs a common mode feedback (CMFB) circuit to keep the output common mode tightly controlled. In this work we propose the reuse of the CMFB circuit of FDAs as an embedded checker to ease the test of the whole amplifier, increasing the observability of faults occurring either in the amplifier or in the CMFB block. Catastrophic and parametric faults are injected into these two circuits by means of SPICE simulations, considering a 0.18µm FDA as case study. Transient and DC (Direct Current) tests are performed and the fault coverage is evaluated. Simulation results point to high fault coverage, while only the common mode feedback signal needs to be monitored. This way, a low-cost and low area overhead test methodology is achieved with affordable test time.
... Fully differential amplifiers are largely used in mixedsignal integrated circuits because this type of circuit presents several advantages, if compared to single-ended amplifiers, such as increased immunity to external noise, increased output voltage swing for a given voltage rail and reduced even-order harmonics [10]. However, FDAs usually need an extra block, known as common-mode feedback (CMFB) circuit, to guarantee the correct functionality of the amplifier [11]. The CMFB circuit is responsible to provide stable levels of output common mode voltage over all operating frequency range of the amplifier [12]. ...
... The circuit studied in this work consists of a single stage FDA. The amplifier was designed considering the 0.18µm process from X-FAB [11]. Both the amplifier and the CMFB schematics are shown in Figures 2 and 3, respectively. ...
... and 3.07mV, respectively. The transistors sizes of the FDA and CMFB blocks and the bias current Io can be obtained in [11]. B. Testing of FD Amplifiers using CMFB circuit Checkers are special blocks usually employed in on-line testing of both digital and analog circuits. ...
This paper presents a simple and low-cost test methodology applied to fully differential amplifiers (FDAs). This kind of amplifier needs a common mode feedback (CMFB) circuit to keep the output common mode tightly controlled. In this work we propose the reuse of the CMFB circuit of FDAs as an embedded checker to ease the test of the whole amplifier, increasing the observability of faults occurring either in the amplifier or in the CMFB block. Catastrophic faults are injected into these two circuits by means of SPICE simulations, considering a 0.18μm FDA as case study. Transient and DC (Direct Current) tests are performed and the fault coverage is evaluated. Simulation results point to high fault coverage, while only the common mode feedback signal needs to be monitored. This way, a low-cost and low area overhead test methodology is achieved with affordable test time.
