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This paper deals with the design and optimization of two-stage CMOS Low Noise Amplifier (LNA) for WLAN applications. IEEE 802.11n WLAN standard provides up to 600 Mbps speed with 40 MHz channel bandwidth and high throughput. The receiver of these WLAN applications requires LNA with higher gain and minimum Noise Figure (NF). Elephant Herding Optimiz...
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Recent advances in wire-like communication channels without a physical wire has seen the emergence of wireline-like broadband channels but with atypical high loss. Communication links using such channels (e.g. Proximity Communication, Human Body Communication) are typically broadband, like wireline systems but noise-limited like wireless systems. H...
In this paper, a CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented. The proposed CMOS LNA is designed using common-gate (CG) topology at the first stage to achieve ultra wideband input matching. The common-gate has been cascaded with common-source (CS) current-reused configuration to enhance the gain and noi...
A 160 MHz bandwidth 90° active RC–CR phase shifter with integrated on-line amplitude locked loop (ALL) calibration targeted to 802.11ac 5 GHz wireless local area network (WLAN) applications is presented in this paper. The quadrature phase shifter is a key component for transceivers employing the Hartley image rejection architecture. The passive RC–...
In this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from low frequency to-5.5-GHz in the inver...
Citations
... In the second one, multiple channels are sensed simultaneously. 17 In the second condition, the optimization problem arises, and it can be converted to a solvable convex optimization problem. 18 The sub-problems can be solved by employing special matrices and reformation techniques. ...
The main objective of cognitive radio network is to provide flexible spectrum management, by permitting the secondary users (SUs) to temporarily access the licensed spectrum in the absence of a primary user. In the existing backward induction approach, each SU performs spectrum sensing and consequently reports the sensing details to the centralized controller. In the proposed work, an adaptive cluster‐based heuristic approach (ACBHA) with cooperative spectrum sensing (CSS) scheme has been proposed for cognitive radio medium access control networks for 5G applications. To identify the availability of unused spectrum, the proposed CSS‐based ACBHA algorithm adopts a cluster‐based selection scheme. Simulation results show that the proposed CSS‐based ACBHA provides a better result compared with existing techniques. The performance parameters such as false alarm probability, the probability of detection, spectrum sensing time, slot length, noise density have been analyzed using MATLAB R2012a. The main objective of cognitive radio network is to provide flexible spectrum management, by permitting the secondary users to temporarily access the licensed spectrum in the absence of primary user. In the proposed work, an adaptive cluster‐based heuristic approach (ACBHA) with cooperative spectrum sensing (CSS) scheme has been proposed for cognitive radio medium access control networks. Simulation result shows that the proposed CSS‐based ACBHA provides a better result compared with existing techniques.
... Hence, there is a severe obligation to control the SCE and a more proficient device structure to improve the nanoscale performance improvement. Recently, the optimized low-noise amplifier designed at 90 nm technology [26] can also be implemented with CMOS technology progress to operate at 5G frequencies. All these factors lead to the FinFET device structure alternate to the scaled CMOS logic in 22 nm and beyond this technology [4,5,7,25,38]. ...
A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating-aware energy-efficient ALU is proposed using this adder and signal gating circuit. An adaptive signal gating is applied according to the current ALU operation based on the particular operation corresponding control word. The input signals to the other blocks are gated such that the proposed intelligent signal gating scheme customizes the overall power utilization of the proposed ALU. The proposed ALU has been implemented using 20 nm FinFET PTM models. The total power consumption of the conventional FinFET ALU to execute all eight operations is 619.55 µW, whereas the proposed ALU consumes 225.53 µW only. The average power consumption of the traditional FinFET ALU is 77.44 µW per operation, while the proposed low-power ALU needs 28.19 µW only. The maximum amount of total and average power that the proposed scheme can optimize is 63.59%.
... While calculating the ratio in Eq. (11), the input and output voltages of both of these devices are considered. Equations (12) and (13) are multiplied to get (11). ...
... The comparison shows that the proposed LNA has less power consumption than the other works. The Figure of Merit (FoM) is calculated by considering the gain, bandwidth, noise figure, power consumption and input return loss [12]. Since the LNAs of different technology nodes are considered for the comparison, the normalized input impedance is calculated from the input return loss, and it is used in the FoM calculation as in Eqs. ...
This brief proposes a two-stage cascoded CMOS LNA with common drain envelope detection based power reduction method for the 5G applications of 28 GHz frequency. Dual inductive peaking and stagger tuning techniques are involved to get a 3 dB bandwidth of 2.25 GHz from 26.75 to 29 GHz. Besides, 22 dB of gain is provided by the proposed LNA. Inductive source degeneration helps to reduce the Noise Figure (NF) of the first cascoded stage, and a 2.3 dB of NF is observed in the LNA. The primarily amplified signals from the first cascoded stage are fed to the envelope detector and the second cascoded stage. When the RF signal is received, the envelope detector output will be high, and it turns on the second cascoded stage. In the existing method, the combination of a diode-connected transistor, low pass filter and buffer has been used for the envelope detection. A common drain transistor with an active resistor and capacitor is used in the envelope detection of the proposed method. Here, the power consumption of the LNA is reduced by 25.26% at the sleep mode. The proposed LNA consumes 9.5 mW and 7.1 mW of power from a 1.5 V supply at the active state and sleep state respectively. It requires 0.1235 mm2 of core area in 90 nm technology. Moreover, the behavior of the circuit under process corner variation and temperature variation is analyzed, and Monte–Carlo analysis is performed.
... Therefore, the low-noise amplifier (LNA) described in this paper was designed in a MEMS-compatible 0.35 lm XFAB process that was available for this research. Common-source (CS) amplifier topologies provide high gain in a narrow bandwidth, which is generally suitable for numerous standards with carrier frequencies around 2.4 GHz [10][11][12][13]. A matching network for a CS-LNA topology can be realized with a simple combination of capacitors and inductors at the input [14,15]. ...
A low-noise amplifier (LNA) topology with tunable input matching and noise cancellation is introduced and described in this paper, which was designed and optimized to interface with a magnetoelectric (ME) antenna in a 0.35 µm MEMS-compatible CMOS process. Compared to conventional antennas, acoustically actuated ME antennas have significantly smaller area for ease of integration. The LNA was simulated with an ME antenna model that was constructed based on antenna measurements. Input matching at the LNA-antenna interface is controlled with a circuit that varies the effective impedance of the gate inductor using a control voltage. Tunability of 455 MHz around 2.4 GHz is achieved for the optimum S11 frequency with a control voltage range of 0.3–1.2 V. The proposed LNA has a noise cancelling feedback loop that improves the noise figure by 4.1 dB. The post-layout simulation results of the LNA show a 1-dB compression point of – 7.4 dBm with an S21 of 17.8 dB.
... Noise of the CS first stage of input matching network is the dominating factor in deciding the performance of the overall noise figure. So in this section simply the noise added is derived here [19] . f is the noise bandwidth [1,20,21] . ...
... Previously, many authors were worked on the optimization and analysis of low noise amplifier. Following reference [1,11,13,16,18,19] authors were worked for the optimization of LNA, but compared with above-cited reference, the work gets achieved minimum noise figure, power gain should be maximum and it also conclude that input and output return loss coefficient are matching i.e., S 11 and S 22 s-parameter values are almost equal, which shows perfectly matching network, and it gives minimum noise figure. Table 1 illustrated performance summary of this designed LNA compared with other cited LNAs. ...
This article deals the design and analysis of CMOS RF receiver front-end with the optimization of single-stage and two-stage low noise amplifier (LNA) for wireless applications. The low noise, high gain and better linearity for 3–10 GHz ultra wideband (UWB) wireless applications realized in 45 nm CMOS technology. The novelty of a single-ended and cascaded CMOS LNA designs for multi-standard purposeful for reconfigurable applications. The proposed LNA espouse entire circuit simulations investigation of the results in the center frequency of 3.4GHz. The admirable power gain (S21) is 32.5 dB with high reverse isolation (S12) of<−43.2dB; the preferable noise figure (NF) obtained as 0.9 dB. The perfect matching of input-output impedance for stability has measured to significantly input-output reflection coefficients S11=−11.6dB,S22=−10.0dB respectively while consuming only 11.8 mW from a 1 V supply.
This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.
A 28 GHz two stage low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. The envelope detection circuit turn‐on the second half of the LNA by the RF signal input received at the first stage. The default gain is increased (31.53%) by the tunable negative feedback capacitor circuit of the LNA with the control voltage from 0 to 1 V. In addition, 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB. The first stage of the LNA is designed with the inductive source degeneration for the noise reduction, and the multiple‐gate topology is involved in the second stage to improve the linearity. The third‐order input intercept point and the noise figure of the LNA are −7 dBm and 2.86 dB, respectively. When the second stage is turned‐on and turned‐off the LNA consumes 7.4 mW and 5.8 mW of power, respectively, from the 1 V supply. The proposed LNA requires 0.19 mm2 of core area. The performance of the LNA under process corner variation and temperature variation are analyzed. A 28 GHz two stage variable gain low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. A 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB.
With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5[Formula: see text]GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5[Formula: see text]GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65[Formula: see text]nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64[Formula: see text]dB while consuming 8.18[Formula: see text]mW of power from a 1.2[Formula: see text]V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67[Formula: see text]dB and the corresponding IIP3 is 9.44[Formula: see text]dBm at 5[Formula: see text]GHz from the pre-layout simulations.
A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely [Formula: see text]. Fabricated on a 0.18[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves [Formula: see text][Formula: see text]dB total harmonic distortion [Formula: see text] with a loudspeaker load of 100[Formula: see text]ohm while operating from a 1.2[Formula: see text]V supply and being subject to a 1[Formula: see text]kHz sinusoidal input.
Purpose
This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements.
Design/methodology/approach
The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm.
Findings
All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR).
Originality/value
The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.
