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Schematic of the conventional level shifter.
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This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal i...
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... This project deals with the design of level shifter which allows compatibility between different blocks of system-on-chip (SoC) designs with different voltage requirements, along with optimized device parameters delay and power dissipation. The CMOS level shifters are typically implemented using either of the two approaches, by using current mirror or Differential cascade voltage switch (DCVS) [6]- [10]. The Fig. 1 shows current mirror-based level shifter, a semi static current mirror is used to limit the current flow, the current is copied from one active node to another. ...
Level shifter plays an vital role in multiple supply voltage techniques which creates a path between processors, sensors or broads of different voltage levels, it converts the input logic levels or voltages below the VTH of the transistor to the higher acceptable levels depending upon the system requirements. So, it is necessary to design a level shifter circuit which provides high performance. Power consumption and delay are the key features which determines the performance of a level shifter. This project mainly focuses on designing the level shifter using regulated cross coupled pull up network which helps in utilizing less power and enhancing the speed of the circuit. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.
... In moderate-speed mixed-mode circuits, partitioning the design into apart supply voltage (V DD ) domains has referred to as an energy-efficiency method. This facilitates lowering dynamic power as the major term of total power, because it quadratically depends on the V DD level [4], [5], [6], [7], [8]. To provide, the time-critical sections are powered at a high supply level (V DD−High ), whereas non-critical blocks run at a low supply level (V DD−Low ). ...
... This circuit has bidirectional level conversion, but using the static gates results in static power consumption. References [4] and [5] use a current generator to suppress the pulling-up current during the fall transition. In [4], during the transition Low-to-High, the short circuit current flows and increases static power. ...
... In [4], during the transition Low-to-High, the short circuit current flows and increases static power. In [5], the transition times may increase largely, the current generators are switched ON for a long time, and the power consumption increases. This brief presents a VLS that can convert the input voltages lower than the nominal threshold (V TH ) to the suprathreshold voltages, it is a robust, energy-efficient, and fast architecture. ...
This brief presents a robust and energy-efficient voltage level shifter (VLS) for wide-range conversion from the subthreshold to the suprathreshold regime. The proposed VLS contains a new logic mismatch detection circuit to address the exist contention current of the conversion stage. A power reducer circuit is introduced to increase the drivability of pull-up and pulldown devices in linear and cut-off regions and further energyconsuming improvement. The proposed VLS is simulated using a 0.18-lm process, the minimal convertible voltage is 0.2 V (deep subthreshold region) for the input signal. Post-layout simulation considering process voltage temperature (PVT) variations proves the proposed VLS outperforms previous designs in several aspects. The results report the consuming energy of 38.5 fJ per transition, a static power of 73.4 pW, and a delay of 14.4 ns when converting range is 0.4 V to 1.8 V. The proposed VLS occupies a 59.98-lm2 silicon area.
... Structure of the voltage level shifter is shown in Fig. 6 (b), which is a conventional structure utilizes positive feedback for increasing the operation speed [32]. By the way, the current consumption of the Digital part of the circuit is about 20.4 pA. ...
In this paper, an analog current-mode circuit with low power consumption and low area is designed and implemented to detect the QRS complexes from the ECG signal. An efficient algorithm is proposed for this purpose which uses the energy operator. This algorithm is fully implemented in the analog domain with the transistors operating in the subthreshold region, resulting in ultra-low power consumption. The proposed method is evaluated with the data contained in the standard MIT-BIH arrhythmia database and reaches the acceptable values of 98.53% for the average accuracy, 99.41% for sensitivity and 99.13% for positive prediction. The proposed circuit is implemented in 0.18 μm CMOS technology with a power supply of 1.8 V. Using this circuit, there is no need to use an analog-to-digital converter in the detector system, which can lead to more reduction in the power consumption and area of the system. With power consumption of 15.77 nW and area of 0.078 mm², this circuit is suitable for using in wearable and implantable applications.
... The SCG-based LS (SCG LS) offers wider input voltage conversion with diminished contention issue; however, it consumes higher static power. Conversely, dynamically controlled current generator [3] alleviates the static current problem, but it causes larger delay and consumes more energy. ...
... The schematic and operation of the proposed HPLS is presented in Sect. 3. Section 4 discusses the simulation results, and the paper is concluded in Sect. 5. Figure 1a shows the structure of WCMLS which has a feedback device MP3 to control the static current flow when the Low-to-High (L → H ) transition occurs. ...
Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 \(\upmu \)m\(^{2}\) (12 \(\upmu \)m \(\times \) 17 \(\upmu \)m).
... We have added an additional bias circuit to the mixed threshold current mirror approach [9] to prevent leakages and voltage swings. The primary disadvantage of stated circuit is that the associated current generators would raise the level shifter's power utilization [10]. In [11] below-threshold voltage apparatus are employed to decrease delay, whereas high-threshold voltage devices reduce power dissipation. ...
... Accordingly, the number of the transistors is increased and the speed of the circuits is degraded. The design of (DSLC) in [19] employs dual supply voltages. In this LC, when the input signal is at logic '0', the transistors in the pull-up path turned ON and the drain node of the input transistor is charged. ...
... Furthermore, as SSLC2 doesn't work at input signals with voltage swing lower than 0.6V, it is not considered as a lowvoltage design. As stated before, in DSLC [19] when the input signal is at logic '0', the incomplete voltage at the input node of the output inverter turns ON the nMOS transistor of the output inverter, but it is not able to turn OFF its pMOS transistor and consequently power dissipation increases. ...
... Although the SSLC4 of [8] has less power consumption as compared to the all designs of [16,17,18,19,20], but has highest delay compared to the designs of [17,18,19,20]. However, in the proposed SSLC, by utilizing dualchirality CNTFETs, source biasing and decreasing the DIBL effect, the power consumption and PDP are considerably reduced. ...
Multi-VDD design is one of the most effective lower-power design techniques. Multi-VDD VLSI circuits require voltage level converters to prevent high static power dissipation between different voltage islands. As the level conversion step imposes additional power and delay to the design, it is very important to optimize the level converter circuits for minimum power-delay product (PDP). This paper presents an energy-efficient single supply level converter (SSLC) based on carbon nanotube FET (CNTFET) for near threshold dual-VDD circuits. CNTFET as an emerging nanotechnology is suitable for low-power and high-performance circuits design. The proposed SSLC is utilized in the structure of a modified low-power parallelized dual-VDD multiplier. Insertion of the proposed SSLC at the output stage of the multiplier significantly reduces static power and enhances the output driving capability. In the proposed SSLC, dynamically controlled source-body voltage reduces the drain-induced barrier lowering (DIBL) effect. In addition, using dual-chirality CNTs leads to optimum static power and energy consumption. The simulation results, obtained using the Stanford CNTFET HSPICE model at 32nm feature size, indicate the superiority of the proposed dual-VDD parallel multiplier utilizing the proposed SSLC in terms of power and power-delay product (PDP) as compared to the single supply multiplier. It is worth mentioning that the proposed low-power multiplier improves static power, average power and PDP by almost 41 %, 42% and 33%, respectively, while maintaining almost the same throughput as compared to the single-supply multiplier.
... A low-power latch-based LS is presented in [40]. In this topology, the MOS transistors of MP6 and MP7 are added on the pull-up network in their diode configuration to mitigate any strong contention. ...
... At the same time, Cp exhibits its highest parasitic capacitance. When VA gradually increases, the MP2 and MP4 go into the triode region which decreases the parasitic capacitance at node A. It should be noted that the gate-source / gate-drain parasitic capacitances of a MOSFET are dominant (other parasitic capacitances are negligible) and are given by Cgs=Cgd=CO/2 in the triode region, and by Cgs=2·CO/3 in saturation, where CO is the total gate capacitance of the MOSFET [40]. Thus, Cp follows a descending curve when the VA increases when IN="1". ...
A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 μm CMOS technology occupies a silicon area of only 25 μm×25 μm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, V
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... In previous papers, various methods have been employed to do this. In [3] the pull-up strength is reduced by using a self-adapting pull-up network and a split input inverting buffer. In [4] a regulated crosscoupled pull-up network is used. ...
... DCVS with decreased pull-up strength[3] Proposed level shifter III. PROPOSED LEVEL SHIFTERFigure 4shows the schematic of the proposed level shifter. ...
A fast voltage level shifter (LS) with zero static and very low dynamic power consumption is presented. It is built upon a differential cascade voltage switch (DCVS) by regulating the pull-up strength of the cross-coupled pair resulting in increased speed of operation. The LS can convert voltage signals in deep sub threshold domains to higher supply voltages. The output of the level shifter is rail to rail across process and temperature. Simulation of the proposed LS in 130 nm CMOS technology shows that the LS can function for inputs as low as the threshold voltage of input NMOS. The delay and dynamic power dissipation for a level shifting input voltage of 0.8V to 4.5V at an input frequency of 1 MHz are 6ns and 243nW respectively.
... Circuits, Systems, and Signal Processing CM structure [2] with self-control mechanism by detecting output error [3,14] or controllable current source with diode-connected level shifter [10]. Even though this method produces better static power performance, it consumes larger switching energy and larger delay due to additional devices. ...
This paper proposes a high-speed and energy-efficient low-voltage current mirror-based level converter (LCM LC) which can perform a wide-range conversion of a subthreshold input signal (180 mV) to an above-threshold output signal (1.2 V). The proposed level converter utilizes low-voltage current mirror (LCM) circuit with high-threshold-voltage (hvt) PMOS devices in the pull-up network, which drives a switching current from high supply rail to output node during the high-to-low transition of an input signal to ensure wide-range conversion. The driving capability of the pull-down network in LCM LC is increased by employing inverse-narrow-width-effect (INWE)-aware low-threshold-voltage (lvt) NMOS devices in order to perform a high-speed operation. This level converter employs multi-threshold CMOS devices and is implemented in 45 nm technology using Cadence Virtuoso. The LCM LC exhibits a delay of 16.4 ns, energy per transition of 28.1 fJ and static power of 412 pW which are observed using Spectre circuit simulator for the target conversion from 0.2 to 1.2 V at a signal frequency of 1 MHz.
... Since a large number of LSs are needed for any system, LS that consumes low static and dynamic power with minimum propagation delay must occupy a small silicon area. [14][15][16][17][18][19][20][21][22][23] Hence, in this article, we propose a low power-delay product (PDP) and power-efficient voltage up LS based on a combination of a current mirror (CM) and cross-coupled pMOS pairs in a pull-up circuitry. The designed LS dramatically reduces power consumption and operates effectively for a wide range of V DDL values. ...
In this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra‐low‐power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low‐level input voltages to the high supply voltage levels. The results obtained from post‐layout simulations in a standard 180‐nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (VDDL) of 0.4 V and nominal supply voltage (VDDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.
