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In this paper we present a low power interface circuit with the new approach of current mode successive approximation (SAR) ADC for biomedical implantable devices application. The circuit includes band pass filter, Gm and current mode SAR ADC. The SAR ADC is a low power circuit that is composed of current mode S/H, current mode comparator, current...
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Context 1
... shown in Fig. 5, to achieve better matching between current sources in higher bits, several parallel transistors with same size as the LSB transistor are utilized instead of one ...
Context 2
... shown in Fig. 4, when the transmission gate is closed, the circuit is at track phase in which I S tracks I in . In holding mode, the transmission gate is open and I S holds the constant value of I in . This value depends on charge of C1 at the tracking mode. The critical problem in this S/H circuit is reduction of voltage on C1 due to the leakage current in the transmission gate. Effect of the leakage current can be decreased by increasing size of C 1 . But choosing big capacitors results in higher power consumption and larger chip area. Therefore, there is a compromise between the power consumption, area and accuracy of the S/H. The conventional current comparator circuit utilizes two cascaded inverters. The input current collects in gate-source capacitance of first inverter, so the input and output voltage of the inverter is dependent on difference between I S and I ref . Second inverter produces the logical level for using in the register circuit. To reduce the power consumption of the comparator when difference between the input current and the reference current is low, two diode connected transistors are added to conventional current comparator (Fig. 4). Therefore, drain-source voltages of M p1 and M n1 are reduced to decrease the first inverter current. In this current mode ADC, cascode current mirrors are used to obtain high output impedance. But, using this topology reduces the voltage swing and hence, lower current could be mirrored in this design. Also, to decrease the mismatch between threshold voltage of P-type and N-type transistors, two kinds of current mirrors (P-type and N-type) are used (Fig. 4). In this work, a current-mode digital-to-analog converter (DAC) is utilized (Fig. 5). The DAC current is produced by mirroring the reference current I DAC . The LSB current (I LSB ) is 500pA, so quantization levels are 0.5nA, 1nA, 2nA, 4nA, 8nA, 16nA, 32nA and 64nA. Also, full scale current I full-scale is defined ...
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Citations
... The ADC in Kramer et al. (2015) represents a non-TI, high-speed and high-resolution CS-DAC in SAR based on the same concept in Doris et al. (2011). Maghsoudloo et al. (2012) presents a low-power interface circuit with CM-SAR ADC for biomedical implantable devices application. The circuit incorporates a currentmode S/H into the Gm stage as an ADC front-end, i.e. the sampling process is performed after the Gm stage. ...
In this paper a new sensor interface using current mode approach is
presented for biomedical applications. The proposed sensor interface utilises a
low-power current-mode comparator, an 8 bit current mode successive
approximation analogue to digital converter (SA-ADC), an adaptable bandpass
filter as well as a highly linear transconductance amplifier (Gm). The Gm
and current mode SAR ADC are designed in a way to achieve minimum power
consumption. The circuit is simulated in 0.18 μm CMOS technology with
supply voltage of 1.8 V. At 400 KS/s sampling frequency, the total power
consumption and total harmonic distortion of the system are obtained equal to
2.2 μW and 45.2 dB respectively. The simulation results demonstrate the
effectiveness and superiority of the proposed circuit in comparison with the
conventional circuits.
... The ADC in Kramer et al. (2015) represents a non-TI, high-speed and high-resolution CS-DAC in SAR based on the same concept in Doris et al. (2011). Maghsoudloo et al. (2012) presents a low-power interface circuit with CM-SAR ADC for biomedical implantable devices application. The circuit incorporates a currentmode S/H into the Gm stage as an ADC front-end, i.e. the sampling process is performed after the Gm stage. ...
In this paper a new sensor interface using current mode approach is presented for biomedical applications. The proposed sensor interface utilises a low-power current-mode comparator, an 8 bit current mode successive approximation analogue to digital converter (SA-ADC), an adaptable bandpass filter as well as a highly linear transconductance amplifier (Gm). The Gm and current mode SAR ADC are designed in a way to achieve minimum power consumption. The circuit is simulated in 0.18 μm CMOS technology with supply voltage of 1.8 V. At 400 KS/s sampling frequency, the total power consumption and total harmonic distortion of the system are obtained equal to 2.2 μW and 45.2 dB respectively. The simulation results demonstrate the effectiveness and superiority of the proposed circuit in comparison with the conventional circuits.
A new external current sensing circuit with baseline compensation for the active matrix organic light emitting diode (AMOLED) display is developed herein to achieve the sensing precision of 0.5 nA in pixel with 7 µs of settling time. Current sensing circuit incorporates a new push–pull transient current feedforward whereas the current analog to digital converter (CADC) based digital baseline current compensation incorporates an 11-bit current digital-to-analog converter, a current comparator and a digital control circuit with an 11-bit successive approximation register. The proposed integrated mixed signal IC drives a 6T1C pixel-based AMOLED panel with one horizontal time of 7.7 µs at a scan frequency of 60 Hz. The design readout chip can simultaneously sense and compensate TFT baseline current variation. The readout circuit and the baseline compensation circuit are implemented in the integrated chip with chip area of 125 μm × 46 μm and fabricated via TSMC T18 process. With the standard 3.3 V supply, experimental result shows that the overall power consumption of the chip is 988 µW watt. The minimum LSB current for the CADC is 10 nA and the maximum achievable sampling rate is 500 KS/s. The measured INL and DNL of CADC is 0.84 and 0.98 respectively. Despite of heavy data line parasitic capacitances (2.6 KΩ/20 pF) of the AMOLED display, experimental results show that the proposed circuit can sense 0.5 nA current within 7 µs of settling time. The sensing precision of 0.5 nA within 7 µs are the best among all reported literature to date whereas the current sense range (0.5–500 nA), system sampling rate (142 KS/s), INL (0.84) and DNL (0.98) of the CADC is approximately comparable among all reported.
This paper deals with the design of a SAR-ADC with 8-bit resolution suited for bio-medical application. The design of the key components of the SAR ADC namely, DAC, Comparator and Sample and Hold circuit (S/H) has been carried out using current mode approach with the DAC operating at sub-threshold regime. The input current range is 10nA to 2.57μA with 10nA as the LSB. The circuit has been designed in UMC 180nm technology Twin-Well Process.
