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This paper presents a fully digitally controlled low dropout linear voltage regulator (LDO). It is implemented in a 65 nm low power CMOS process. The input voltage range covers 3 V to 5 V while the output voltage is 2.87 V with a nominal load of 150 mA. The digital controller was implemented using VHDL, automated synthesis- and place & route tools....
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... в данном случае напряжение, поступающее от выпрямителя) очень близко по значению к этому выходному напряжению. Несмотря на более низкую эффективность (по сравнению с импульсными стабилизаторами) стабилизаторы с малым падением напряжения отличаются меньшими размерами, меньшей стоимостью внешних компонентов, малыми шумами и малыми пульсациями выходного напряжения [182][183][184]. ...
... По этой причине в настоящее время в микромощных интегральных приложениях получили распространение стабилизаторы, полностью или частично построенные на основе цифровых компонентов [187,191,192]. Помимо возможности работать при малых напряжениях стабилизаторы на основе цифровых компонентов отличаются малой чувствительностью к шумам, малой чувствительностью к изменениям температуры и параметров процесса [37,182], малой потребляемой мощностью [186], технологической масштабируемостью и возможностью совместимости с другими технологическими процессами [182,193]. Несмотря на то, что большинство интегральных стабилизаторов с малым падением напряжения способны функционировать в отсутствии внешнего конденсатора [181,193,194], стабилизация напряжения в условиях цифровой нагрузки (микроконтроллер, микропроцессор) приводит к значительным выбросам тока, и, как следствие, требует минимальной встроенной емкости для поддержания напряжения питания в пределах определенной погрешности [191]. ...
... По этой причине в настоящее время в микромощных интегральных приложениях получили распространение стабилизаторы, полностью или частично построенные на основе цифровых компонентов [187,191,192]. Помимо возможности работать при малых напряжениях стабилизаторы на основе цифровых компонентов отличаются малой чувствительностью к шумам, малой чувствительностью к изменениям температуры и параметров процесса [37,182], малой потребляемой мощностью [186], технологической масштабируемостью и возможностью совместимости с другими технологическими процессами [182,193]. Несмотря на то, что большинство интегральных стабилизаторов с малым падением напряжения способны функционировать в отсутствии внешнего конденсатора [181,193,194], стабилизация напряжения в условиях цифровой нагрузки (микроконтроллер, микропроцессор) приводит к значительным выбросам тока, и, как следствие, требует минимальной встроенной емкости для поддержания напряжения питания в пределах определенной погрешности [191]. ...
... Therefore, the area of the LDOs should be reduced. In recent years, digitally controlled LDOs are presented for their advantages of low sensitivity to process variations and low voltage operation [12,17]. In [12], the analog-to-digital converter (ADC) and the digitalto-analog converter (DAC) blocks are still analog circuits. ...
... In recent years, digitally controlled LDOs are presented for their advantages of low sensitivity to process variations and low voltage operation [12,17]. In [12], the analog-to-digital converter (ADC) and the digitalto-analog converter (DAC) blocks are still analog circuits. In the analog circuits, it is difficult to reduce the area as the fabrication technologies advance. ...
This paper presents a Multiple Reference All Digital Low Dropout Regulator (MRADLDO) utilized 98.1 % current efficiency and 100 mA maximum load current. MRADLDO performs selectable different reference voltages to apply in the multi VDD core applications as well as Dynamic Voltage and Frequency Scaling issues. This improves control on delay, speed and power of the subject circuits. This structure has the fast response to variation in load or variation in selection voltages. Maximum required time for settling output, in the worst case, is less than 256 ns. Furthermore, a self calibration structure is embedded for the sake of decreasing the steady-state time. While changing the output voltage (Vout), reference voltage (Vref) is been switched accrued, there is a parallel access to control unit data in order to load initial value for the LDO controller shift registers from a simple embedded memory. To show the effectiveness of the proposed design, it is applied on ARM1176JZF-S processor supply via producing four required levels of voltage as high level (HL)@1.21 V, medium level ML@1.14 V, low level LL@0.99 V and sleep mode SM@0 V. Likewise, a comparison between two proposed multi references LDO such as MRADLDO and analog multiplexer is utilized to illustrate the effectiveness of the proposed MRADLDO circuit.
... Thus, the area of the LDOs should be reduced. Over recent years, digitally controlled LDOs are reported for their advantages of low sensitivity to process variations and low voltage operation [11,14]. In [11], the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) blocks are still analog circuits. ...
... Over recent years, digitally controlled LDOs are reported for their advantages of low sensitivity to process variations and low voltage operation [11,14]. In [11], the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) blocks are still analog circuits. When using analog circuits, it is difficult to reduce the area as the fabrication technologies advance [14]. ...
Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm² of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.
A low quiescent current digital low-dropout (DLDO) voltage regulator with fast-transient response time is proposed for self-powered wireless sensor applications operating at near/subthreshold supply voltage. The D-LDO regulator incorporates both hill-climbing and binary search algorithms (HCBS) in the control logic, thus leveraging on each other's strengths to minimize the output voltage's ripple and the quiescent current during the steady-state period as well as output voltage's spike and response time during the transition period. Additional features such as hysteresis mode control and freeze mode control are incorporated into the system to improve the performance of the D-LDO regulator. A dynamic comparator is proposed for the near/subthreshold supply voltage operation, which minimizes the voltage error and improves the maximum operating frequency. Fabricated in 130-nm CMOS technology, the D-LDO regulator regulates the output voltage V-OUT from 350 to 1150 mV, while the input supply voltage V-IN ranges from 450 to 1200 mV. At a V-OUT of 450 mV, V-IN of 500 mV and an operating frequency of 10MHz, the regulator delivers 1500-mu A load current with IQUIESCENT of 8.9 mu A and a transient response time of 1.6 mu s. The maximum current and power efficiencies reach 99.9% and 89.9%, respectively. The measured line regulation and load regulation are 1.6 and 0.6 mV/mA, respectively.
This paper presents a digitally assisted low-dropout voltage regulator. In lieu of the analog error amplifier, the proposed structure uses an analog-to-digital converter, a digital-to-analog converter, and a digital processor. It offers flexibility in terms of stability and regulation accuracy. The measurement results verify the performance of the proposed structure.
A digitalized switch-mode LED driver is implemented using a 0.35μm high voltage process, which featured by no use of any ADCs. The comparison result between the output current and the desired current causes the counter to increase or decrease its binary value which determines the duty ratio of the PWM signal. This PWM signal controls switching devices. A delay routine added in the counter prevents oscillation of the counter value owing to a high speed clock.
The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.
A new ADC-free digital-control switch-mode LED driver with 1MHz switching frequency is presented, which is featured by digital counters, a PWM generator, and current comparators. The digital counter consists of up/down counters with a delay routine. The counter increases or decreases its binary value, depending on comparison result between the output current and the desired current. Then a PWM signal can be generated, which its pulse width is determined by multiplication of the binary value and the clock period. To prevent oscillation of the counter value owing to high frequency clock, a delay routine is added. This designed LED driver is successfully implemented through a 0.35μm 2poly-4metal high voltage process.
This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a ${-}{rm 47}~{rm dB}$ PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.
