Figure - available from: Transactions on Emerging Telecommunications Technologies
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Low‐noise amplifier supports broadband standards with the advantage of low‐power, high‐gain, and low noise figure (NF). The low‐frequency design of this low‐noise amplifier (LNA) is used for multistandard wireless applications and the high‐frequency design of this LNA can be used in millimeter wave radar applications. This LNA is designed at the fr...
Citations
... barrier, and a 2 nm n+GaN/n+AlN/n+GaN cap laye,r and a back bulk on 4H-SiC. The 4H-SiC is selected due to its high resistivity and thermal conductivity [9,10]. From what has been proven by the recent literature, it is noticeable that the temperature in the growth of the GaN device on a 4H-SiC substrate is the lowest compared to that fabricated on a sapphire substrate [11,12]. ...
In this study, a 30 nm gate length double-gate InAlN/GaN on 4h-SiC substrate high-electron-mobility transistor is proposed. Different electrical characteristics such as DC, AC, capacity and noise analysis was performed through TCAD device simulations. The proposed device exhibited maximum drain current of 2.15 A/mm, transconductance of 1308 mS/mm, (350/ 610) GHz of FT/FMAX and maximum noise figure of NFMax=9.5 dB at 1 THz. Thus, the low noise high electron mobility transistor (LNA-HEMT) amplifier has been designed considering main characteristics of power with new structure, in terms of temperature and low noise figure effect. Adopting the backup bulk in the optimization procedure the proposed device obtained an outstanding performance with appropriate low power consumption for GEO satellite application
... Cascoded configuration provides benefits in terms of bandwidth, gain, stability, and impedance matching. 15 Common source (CS) and common gate (CG) configurations are used as the primary amplifier and cascoded amplifier, respectively, in it. The CS amplifier has high voltage and current gain; CG amplifier has high voltage gain and low current gain. ...
... The ratio between V y and V x is calculated by multiplying Equations (12) and (13) as present in Equation (11). In Equation (13), the total transconductance of N M2 and N M3 transistors is calculated as in Equation (15). Similarly, the total gate to source capacitance is calculated as in Equation (14) c gs5 + c gs7 = c gst (14) g mt = g m5 + g m7 (15) The impedance seen from the input side of the N S2 transistor is shown in Equation (16). ...
... In Equation (13), the total transconductance of N M2 and N M3 transistors is calculated as in Equation (15). Similarly, the total gate to source capacitance is calculated as in Equation (14) c gs5 + c gs7 = c gst (14) g mt = g m5 + g m7 (15) The impedance seen from the input side of the N S2 transistor is shown in Equation (16). The overall gain of the second cascoded stage is calculated by multiplying the Equations (10) and (11). ...
A 28 GHz two stage low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. The envelope detection circuit turn‐on the second half of the LNA by the RF signal input received at the first stage. The default gain is increased (31.53%) by the tunable negative feedback capacitor circuit of the LNA with the control voltage from 0 to 1 V. In addition, 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB. The first stage of the LNA is designed with the inductive source degeneration for the noise reduction, and the multiple‐gate topology is involved in the second stage to improve the linearity. The third‐order input intercept point and the noise figure of the LNA are −7 dBm and 2.86 dB, respectively. When the second stage is turned‐on and turned‐off the LNA consumes 7.4 mW and 5.8 mW of power, respectively, from the 1 V supply. The proposed LNA requires 0.19 mm2 of core area. The performance of the LNA under process corner variation and temperature variation are analyzed. A 28 GHz two stage variable gain low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. A 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB.
... It has been stated that an excellent cascade LNA working between 3 and 5 GHz exists. 13 Gain and NF responses are always at odds with one other. Because the low-frequency spectrum is getting increasingly congested with applications, using high-frequency design is becoming more difficult. ...
... The middle stage provided additional gain plus a zero pole cancelation with the help of the capacitive peaking method. However, by implementing the TIA prototype in a 0. 13 BiCMOS was measured, and it resulted in high peaking voltage at 50 GHz of BW. ...
In low noise amplifier (LNA) design, achieving minimum noise figure (NF) and enhanced gain is equally important in the field of communication. The major aim of this design with previous methods are those having implemented in the topology of design like metal oxide semiconductor field effect transistor at common source connection topology, pole‐based transformer boosting, and dual feedback technique. However, these methods fail to reach the desired performance due to their low NF and low gain. In order to overcome these failures and their causes, this article presented a topology in LNA design using a transformer as boosting component to improve the performance of NF and gain for millimeter‐wave applications. It has three common gate stages connected in cascode form, and three transformers are acquired to link the drain to the input signal. Transformers permit radio frequency feeding signal from drain to source, and output from the previous stage is connected to the input of the next stage. This connection increases the gain of the circuit and an enlarged coupling coefficient of value “1,” which minimizes noise. The unilateral coefficient remains to be 1, to make the circuit stable throughout execution. NF value can be minimized by properly selecting conductance coefficient and S‐parameter values. Since the transformer is used to provide feedback in this circuit, stability condition has to be analyzed carefully. Output load value is selected optimum as it creates an impact on the stability of LNA. This topology implemented in LNA design helps to increase the gain by boosting the signal input, and hence, in turn, it increases overall gain performance. Similarly, while executing this optimal LNA design using transformer boosting technique in CADENCE software, this LNA exhibits a minimum NF of 3 dB at 30 GHz and power gain of 12.2 dB at 50 GHz in measurement. Comparatively, the proposed LNA design overruns conventional methods and consumes a power supply of 1.1 V.
As an initial block in the receiver front-end, LNA needs to achieve high gain with minimal noise at high frequencies. LNA designs at 5G communication have drawbacks such as increased noise figure, minimum gain, and poor linearity. A CMOS Low-Noise Amplifier for the frequency range of 30 GHz with optimization technique of current reuse technique and linearization technique is proposed and implemented to obtain maximum gain with reduced noise figure with improved linearity in this paper. The linearization technique improves the input of third-order intercept point (IIP3) of an LNA. The parameters, such as sufficient gain, low noise and enhanced linearity, are considered to design the LNA for wireless 5G communication. The proposed design shows an improvement in gain and lesser noise figure compared to conventional designs. The simulation results show that the proposed LNA provides a maximum gain of 20.6 dB, a noise figure of 3.1 dB and IIP3 of 6 dB at 30 GHz with a power consumption of 6.2 mW from a supply voltage of 1.2 V. The proposed Low-Noise Amplifier is designed and simulated in the 45 nm CMOS technology.
