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Increasing power delivery and performance requirements for next-generation Intel microprocessors has led to the need for a high-capacitance low-inductance decoupling option very close to the die. An embedded array capacitor (EAC) is a large array capacitor embedded in the high-density interconnect (HDI) substrate core and provides a low-inductance...
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Warpage is a critical concern in the microelectronics industry for several decades. It is a root cause of failures during manufacturing processes such as open solder joints. Also the excessive warpage generates the delamination and die cracking which degrade the package reliability. Thus, the accurate estimation of package warpage is one of the imp...
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... To meet most of these requirements, we thought of taking advantage of embedded capacitor materials that have very interesting characteristics and are currently widely used. [17][18][19][20][21][22] The idea presented in this article is to design an original planar capacitor model made of a flexible embedded capacitor material (ECM) as an alternative to the discrete capacitor in a DC/DC converter. We used the embedded capacitor material due to its interesting properties which are summarized by a high capacitance density, low impedance, ultra-thin format, greater damping of electromagnetic waves and good compatibility with printed circuits. ...
In this work, we present the design and fabrication process of an ultra-thin capacitor model, the "planar accordion capaci-tor." This capacitor, which meets the requirements of various fields, was developed at the Plasma and Energy Conversion Laboratory (LAPLACE) of the University Paul Sabatier-France. We used the interesting properties of embedded capacitor materials (ECM) to design this capacitor model. Its design is based on the original way of folding a ribbon of flexible ECM to realize several parallel capacitors on a small surface without connecting wires. The assembly is then subjected to thermo-compression to form a single ultra-thin polymerized element. This process significantly increases the capacitance value and capacitance density, and reduces the dissipation factor. A prototype of an ultra-thin capacitor was successfully manufactured at LAPLACE, and meets the specifications of a buck converter for low power. With a section reduced from 9.3054 cm 2 to 1.01 cm 2 and capacitance density increased from 1.07 nF/cm 2 to 9.88 nF/cm 2 , this capacitor boasts a high resonance frequency of 30 MHz and negligible losses, with a very low dissipation factor of 0.039. The COMSOL Multiphysics simulation showed correct behavior of the potential, electric field, charge density, and uniformly distributed temperature. This design offers many advantages, including reduced dimensions, high resonance frequency, high capacitance density, negligible losses, and low impedance, allowing it to charge quickly, making it a promising capacitor for various industries. We can also modify the folding for smaller dimensions and the desired capacitance value.
... A PCB contains several traditional layers placed between multiple high-density interconnect (HDI) layers [5]. Microvias are used as electrical interconnects among different conducting layers in HDI technology [6], [7]. A significant number ranging from a few thousand to millions of microvias are used on a single PCB. ...
The automotive industry’s increasing dependence on compact electronic packages requires printed circuit boards with robust microvia interconnections. With a focus on minimizing failure rates and reducing costs, automotive manufacturers require that microvia reliability have zero failures. To achieve this, the automotive industry requires identification and understanding of the uncontrollable factors related to substrates that influence microvias during the reflow process. However, conventional studies not accounting for the non-uniform nature of substrates fail to capture the real-time impact of composite substrates on microvias during reflow, highlighting the need for comprehensive substrate analysis. In this paper, we present a detailed finite element model substrate layer to analyze the influence of the substrate material on microvia structures using the design of experiment technique using the Taguchi method. The results showed that the uneven distribution of fiber and resin ratios within the substrate layer affects the microvia structures. Microvias in resin-rich areas are more susceptible to failure with 33% higher stresses than those present in fiber-rich areas. Furthermore, printed circuit board substrate is characterized into different zones based on microvia failure risk levels.
... Therefore, integrating a discrete capacitor into the package causes several problems such as thermal expansion, impedance discontinuity at the terminal of the capacitor, increasing the package profile…etc. To solve these problems, the solution of using the metal layers available in the PCB, package, or on-chip to form the embedded capacitor is proposed [4][5][6]. ...
... The dimensional parameters that are used in equation from (1) to (5) are defined in Fig. 3. ...
... The assembly product quality is determined by many feature quantities. Because of the importance of each feature, assembly product quality is very different [6]. Based on gray theory, a multi-parameter diagnosis method of rolling assembly process for complex products has been developed. ...
Assembly quality affects complex product's performance in high degree because the assembly is the end of manufacture process. In this paper, a comprehensive evaluation and forecast control of various factors affecting assembly failure is presented based on theory of gray system. Firstly, the absolute correlation degree and relative degree of correlation are calculated by using data from assembly process of complex products. Then, the comprehensive correlation degree and rank analysis are obtained with the gray method. Finally, the gray system theory is used in quality analysis and forecast control of a valve manufacturer. The final result indicates that excess amount of leakage is the main factor affecting product quality in accord with the actual situation.
... Using a combination of finite element analysis and fatigue life prediction, the required amount of HDI board reliability testing is reduced, cutting overall development time and cost. to components with increased I/Os and reduced footprint areas (e.g., flip-chip packages, chip-scale packages, and direct chip attachments, as well as 3-D packages using through-silicon vias (TSVs) [1], [2]), and on the package substrate and printed circuit board (PCB) level, to the use of high density interconnects (HDIs) [3], [4]. HDI technology makes use of microvias as interconnects between different conductor layers. ...
... The limit number of cycles to failure under each load was calculated using Engelmaier's fatigue life model based on the total strain range from FEA, that is, ( 1,2,3) i Ni was estimated. From Eq. (7), the applied number of thermal cycles (-55 °C to +125 °C) to failure was derived as 33 12 ...
The increase in the I/O density and the decrease in the size of electronic packages have driven the need for high-density interconnect (HDI) circuit boards that use microvias as interconnects. One challenge for HDI circuit board development is to fabricate microvias without generating voids in deposited copper structures. A parametric study was conducted to investigate the effects of voids on the thermomechanical reliability of copper-filled stacked microvias using 3-D finite-element analysis and strain-based fatigue life estimation. It was found that microvia fatigue life was affected by geometrical void characteristics, such as shape, size, and location; microvia aspect ratio; and dielectric material properties. While voids are defects in copper-filled microvias, the existence of voids is not always detrimental to microvia reliability. For example, a microvia with a spherical void of 8% volume ratio had a 10% longer fatigue life than the same microvia without voiding. On the other hand, large voids decreased the durability of microvias—a 16% conical void resulted in a microvia fatigue life that was only 1.4% of that of a nonvoided microvia. Moreover, microvia aspect ratio is a critical parameter for reliability. The fatigue life of a voided microvia of 0.25 aspect ratio was more than two orders of magnitude longer than the fatigue life of a voided microvia of 0.75 aspect ratio with the same void volume ratio. As an outgrowth of this study, a microvia virtual qualification method is proposed. Using a combination of finite-element analysis and fatigue life prediction, the required amount of HDI board reliability testing is reduced, cutting overall development time and cost.
Transition metal carbides (MXenes) are novel two‐dimensional (2D) nanomaterials with exceptional properties, promising significant impact in applications such as energy storage and conversion, and catalysis. A major barrier preventing the widespread use of MXenes is the lack of methods for assembling MXene in 3D space without restacking, which degrades their performance. Here, we successfully overcome this challenge by introducing a novel material system: a 3D MXene network on a porous ceramic backbone. The backbone dictates the network's 3D architecture while providing mechanical strength, gas/liquid permeability, and other beneficial properties. Freeze casting is used to fabricate a silica backbone with open pores and controlled porosity, a MXene dispersion is infiltrated into the backbone using capillary flow, and the system is dried to conformally coat the pore walls, creating an interconnected 3D‐MXene network. The fabrication approach is reproducible, and the MXene‐infiltrated porous silica (MX‐PS) system is highly conductive (e.g., 340 S·m ⁻¹ ). The electrical conductivity is controlled by the porosity distribution, MXene concentration, and infiltration cycles. Sandwich‐type supercapacitors with MX‐PS electrodes produce excellent areal capacitance (7.24 F·cm ⁻² ) and energy density (0.32 mWh·cm ⁻² ) with only 6% added MXene mass. This approach of creating 3D architectures of 2D nanomaterials will significantly impact many engineering applications.
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Intel's microprocessors are powered by high frequency fully integrated switching regulators implemented on die. Current products use non-magnetic inductors designed in the package substrate. This work investigates the use of magnetic thin film inductors fabricated on silicon wafers as an alternative that improves conversion efficiency while achieving higher inductance per area density. This paper builds on the earlier work done on thin film inductors at Intel and explores the feasibility of using them in a high volume product. A number of different design variations are studied to look at trade-offs between efficiency, saturation characteristics, transient response, and voltage ripple. This is accomplished through a combination of passive measurements using a VNA and active measurements on a fully functioning integrated voltage regulator system.
