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In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing...
Contexts in source publication
Context 1
... that the odd stage number is necessary to keep the XOR function. In order to derive the error threshold value for two-input XOR gates and two-input NAND gates, the circuit schematic shown in Figure 6 is involved. As can be seen, the circuit schematic is a binary tree of cascaded two-input unreliable XOR gates and NAND gates [14,23]. ...
Context 2
... us denote the probabilities of the two inputs of the XOR gate being stimulated by X and Y. Since there are no feedback loops and fan-out in the circuit, the two inputs can be treated as independent. Then, the probability of the output of XOR gate being stimulated is In order to derive the error threshold value for two-input XOR gates and two-input NAND gates, the circuit schematic shown in Figure 6 is involved. As can be seen, the circuit schematic is a binary tree of cascaded two-input unreliable XOR gates and NAND gates [14,23]. ...
Context 3
... order to derive the error threshold value for two-input XOR gates and two-input NAND gates, the circuit schematic shown in Figure 6 is involved. As can be seen, the circuit schematic is a binary tree of cascaded two-input unreliable XOR gates and NAND gates [14,23]. ...
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