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The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL...
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Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. Howe...
![Figure 5. Schematic diagram of function select logic block [30].](publication/355498946/figure/fig3/AS:1082820579590146@1635175952937/Schematic-diagram-of-function-select-logic-block-30_Q320.jpg)
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option....
Resistive random-access memory (RRAM) is essential for developing neuromorphic devices, and it is still a competitive candidate for future memory devices. In this paper, a unified model is proposed to describe the entire electrical characteristics of RRAM devices, which exhibit two different resistive switching phenomena. To enhance the performance...
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... The paper extensively examines the impact of channel length miniaturization on threshold voltage and leakage current, as discussed in [25]. However, challenges related to chirality factor control, fabrication methods, CNT development, and precise CNT placement pose significant obstacles for CNTFETs, as highlighted in [26]. Furthermore, the limited availability of simulation tools for CNTFET devices adds another layer of complexity to the study. ...
Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442nW and 0.323nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.
... One of the major problems with nanoscale devices is their temperature sensitivity, which can have a negative impact on the circuit's reliability and functionality [40]. Due to inverted temperature dependence (ITD) effect, delay decreases with increase in temperature and increases .in ...
Multiplication is a fundamental arithmetic process, although it necessitates more hardware resources. Researchers in advanced technology attempted to boost the speed and lower the power in digital signal processing applications by utilizing multipliers. The majority of digital signal processing applications demanded increased speed. In addition, ternary logic based on CNTFETs is a feasible alternative for Si-MOSFETs. The article proposes a ternary multiplier, which is designed using proposed ternary logical and combinational circuits that includes STI, TNAND, TNOR, and ternary decoder. The proposed and existing designs are simulated, compared, and analysed on the parameters of delay, average power, and noise using the HSPICE simulator. Therefore, the results show 10%, 81% and 81% improvement in delay, average power, and PDP respectively for proposed TMUL. The noise margin of the proposed TMUL is increased up to 54% over existing circuits. The proposed TDecoder, STI, TNAND, and TNOR are 95%, 97%, 81%, and 95% more energy efficient than existing designs, respectively.
... Ternary logic is a subclass of MVL with radix 3 [4]. Ternary logic uses three logical levels, allowing more information to be transmitted over a single channel than binary logic [5]. Replacing binary with ternary logic helps in designing energy-efficient circuits. ...
Ternary logic offers faster response and low power consumption for digital systems, which minimizes the connection complexity, chip size and power consumption. Multi-threshold and geometry dependent properties of CNTFET make it a suitable alternative over the traditional Si-MOSFET for ternary logic circuit implementation. The proposed work minimizes the power dissipation, improves the speed and noise margin for designing efficient ternary circuits. In this article, one ternary decoder and two ternary comparators are designed and analysed. The proposed circuits are simulated and compared with existing circuits using HSPICE Synopsys tool. The proposed ternary decoder shows improvement up to 48% and 74% in power dissipation and power delay product, respectively, as compared to existing circuits. The proposed ternary comparator saves 82% power over other ternary comparators. Noise margin for proposed ternary decoder and ternary comparators is increased to up to 21% and 34%, respectively.
... However, comprehending the intricacies of transport and switching systems presents an ongoing challenge. Numerous attentions were on the nucleation and dissolution of CF; nonetheless, the precise switching mechanism remains somewhat enigmatic [5], [6]. ...
... Alternatively, the expansion of the gap correlates with an escalation in the bias voltage magnitude, as indicated in Fig. 9b. Addressing degradation in ZnO-based RRAM involves a comprehensive understanding and innovative strategies like voltage compliance limits, suitable electrode materials, improved insulating layers, and unique device architectures [1]- [3], [6]. ...
... Therefore, different threshold voltages can be achieved for every circuit implementation by merely adjusting diameter of the CNT, that is determined by the chirality vector (n, m). Therefore, it is possible to alter the threshold voltage of CNTFET by making adjustments to either the chirality vector or the diameter of the CNT [57,58]. Compared to CMOS devices, this fact makes CNTFET a more attractive option for the realization of designs based on ternary logic. ...
... In comparison to conventional designs, a significant reduction in transistor count was demonstrated, along with lower power consumption and improvements in latency and the noise margin [113]. CNTFETs with resistive random access memory (RRAM) were offered as design features for non-volatile ternary logic gates by Zahoor et al [58,[114][115][116][117]. Instead of using huge devices (resistor) to achieve ternary logic gate, the design used activeload RRAM and CNTFET. ...
... (a) Comparison of I-V curve of n-type MOSFET with n-type CNTFET in 32 nm technology for I D -V DS (b) Linear scale I D -V GS[58]. ...
The research interest in the field of carbon nanotube field effect transistors (CNTFETs) in the post Moore era has witnessed a rapid growth primarily due to the fact that the conventional silicon based complementary metal oxide semiconductor (CMOS) devices are approaching its fundamental scaling limits. This has led to significant interest among the researchers to examine novel device technologies utilizing different materials to sustain the scaling limits of the modern day integrated circuits. Among various material alternatives, carbon nanotubes (CNTs) have been extensively investigated owing to their desirable properties such as minimal short channel effects, high mobility, and high normalized drive currents. CNTs form the most important component of CNTFETs, which are being viewed as the most feasible alternatives for the replacement of silicon transistors. In this manuscript, detailed description of the recent advances of state of the art in the field of CNTFETs with emphasis on the most broadly impactful applications for which they are being employed is presented. The future prospects of CNTFETs while considering aggressively scaled transistor technologies are also briefly discussed.
... The interconnects utilized in developing the integrated circuits (ICs) lead to cross-talk, delay and high power [36]. Due to continuous shrinking the channel length of semiconductor device, interconnect became the most crucial to define the IC performance [37]. In recent days, ternary logic is conceived as the best method to avoid the parasitic and delay effects in interconnects. ...
... The RRAM consists of a conductor-insulator-conductor (CIC) shape, and its functionality depends on change in resistance upon the applications of external inputs to gather the binary data. Due to significant advantages such as easy fabrication, simple structure, reduced power, storing the nonvolatile data and suitable with CMOS technology, the RRAM is used for developing the digital logic circuits [11,37,39,40]. Using RRAM, the binary logic schematics are presented in [10,38] and ternary logic schematics are developed in [39]. ...
... Using RRAM, the binary logic schematics are presented in [10,38] and ternary logic schematics are developed in [39]. In recent days, the ternary circuit schematics utilizing CNTFET and RRAM are discussed in [36,37]. In [36], the inverter, NAND, NOR, adders, subtractors and multipliers are developed using CNTFET and RRAM. ...
In this paper, the designs of ternary digital circuits are discussed. The ternary logic is a better choice over conventional logics due its extraordinary offers such as high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented in this paper to design the ternary circuits using graphene nanoribbon field effect transistors (GNRFETs) and resistive random access memory (RRAM). The dimer line of graphene nanoribbon (GNR) is used to control the threshold voltage of GNRFETs. The RRAM is used because it has multilevel cell capacity that enables the multiple resistance state storage in a single cell. The ternary logic basic circuits such as standard ternary inverter (STI), NAND and NOR circuits are proposed. In addition, ternary half adder circuit is designed that helps to develop the complex circuits. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). Furthermore, the obtained circuit performances are compared with carbon nanotube FETs (CNTFETs)-based and RRAM-based circuits. The comparison results show that the proposed GNRFET and RRAM circuits achieved 46.11% of overall performance improvement over the CNTFET and RRAM circuits. Furthermore, line edge roughness (Pr) effect on the proposed STI and half adder circuit performance is investigated. The delay values are increased, and the power and PDP values are decreased for the higher Pr values. The effect of process, voltage and temperature (PVT) variations on proposed STI and half adder circuits is also performed to analyze the performance. It noticed that the proposed STI and half adder circuits show minimum variation on performance for the PVT variations.
... By 2006, MOSFET transistors had reached a nanoscale dimension of 65 nm [6]. In the Nano region, bulk silicon MOSFETs commonly suffer from high parametric variations and increased leakage currents [7]. There have been numerous advances in post-silicon technologies designed to overcome the problems associated with nanoscale MOSFETs. ...
This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder cells. Software simulations confirm the suitable quality of the final images according to the image quality evaluation criteria.
... In the last decade, many ternary circuit designs have been demonstrated using CNFET technology, such as ternary logic gates, memory, and combinational circuits [2][3][4][5][6]. More specifically, several ternary full adders have been proposed [7][8][9][10][11][12][13][14][15][16][17][18]. We compared the performance of these ternary adders with the proposed designs. ...
... This method will generate a high transistor count and PDP, as observed in the following papers: Authors of [7] created a TFA with 412 CNFETs. In [8], the authors presented a TFA with 337 CNFETs and 14 RRAMs (Resistive Random Access Memory). (2) Use algorithms for logic synthesis. ...
... Not using the basic ternary logic gates (STI, TNAND, TNOR), TDecoders, and ternary encoders. Because using the basic ternary logic gates will produce a high transistor count and more energy consumption (compared to [7,8,15]). ...
The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd
and Vdd/2
) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.
... Thus, novel data processing technologies need to be explored to critically address the issue of insufficient computing capacities particularly in "memory" which nowadays constitutes about 60% of the processor area thus constituting for the major target of the designers for device miniaturization. Presently, researchers in nanoelectronics field are focusing their efforts on resistive random access memory (RRAM) which is one form of memristor technology as a feasible option for existing CMOS-based device miniaturization [5][6][7][8][9][10][11][12][13]. The research in RRAM continues to witness a tremendous growth as it is seen as the promising alternative to existing CMOS devices owing to its numerous advantages such as scalability, high data retention, CMOS and 3D integrability, multistate programmability, good endurance, lower power consumption and relatively high speed [14]. ...
The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.
... This popularity is mostly because of its high flexibility in threshold adjustment. Other popular technologies are graphene nanoribbon FET [34,47,60,75,76] and memristor [22,23,26,63,[77][78][79][80]. A fusion of two technologies has sometimes been exploited. ...
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.
