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Schematic of Novel Ripple Carry Adder The Figure 12 shows the schematic of novel ripple carry adder. The RCA employs four novel reversible full adders. The number of constant inputs employed hare is 12. The simulation is performed and tested for various input combinations.
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Background/Objectives: The objective is to reduce the Quantum Cost (QC), Garbage Output (GO) and Gate Counts in the design of the adder by incorporating the Novel Reversible Gates. Methods/Statistical Analysis: In recent day's energy dissipation is the major complex problem in circuit designing in order to recede this problem the reversible logic i...
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Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator wit...
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... In other words, the first step in securing the computer is to encrypt the code to just boot and execute the code you want. Integrity is the deduction to ensure that medicinal information is kept from unauthenticated and unwanted changes and that valuable and worthy individuals are provided with medicinal information where necessary [17] [18]. ...
The main objective of this article is to learn about the obstacles of Internet of Medical Things (IoMT) networks and discover an efficient Quantum Key Distribution (QCT) solution. In this case, analyzing the IoMT network infrastructure will fool the entire backbone of the structure if the system gets into the wrong hands. While analyzing the algorithm, we can create a series of models that can effectively secure the network of the system. So generating or copying the correct private key used by the generator becomes very difficult on the device. The article identifies the various issues of the IoMT network and presents the solutions presented using “quantum key distribution”, as IoMT is the medical revolution that, if something goes wrong, will lead to huge losses in patients’ lives, medical records and economy. The document describes several issues in the IoMT based on findings and presents solutions presented using “quantum key distribution”. This is because the Internet of Things (IoMT) is a medical revolution that has a clear imprint on people’s lives as well as the economies of countries. In any existing IoMT framework, the proposed algorithm can be performed to measure and identify any error in the method.
... Adder using the Peres gate and Novel gates are designed in [7,8]. A more complex circuits like multiplier [9], Master-Slave Flip flops [10], FIR filers [11] and Floating point division units [12] are designed for area efficiency. ...
Reversible computing is a model of computing where the computational process to some extent of degree is reversible. An essential circumstance for reversibility of a computational version is that the relations of the mapping states of transition features to their successors have to always be one-to-one. Reversible logic has emerged as a change in the design technique of conventional logic, ensuing in decrease energy consumption and lesser circuit area. In this work, a design of efficient architecture of the reversible FIR filter structure is presented. Reversible gates such as Fredkin, Peres and PFAG gates are used. The coding was done using Verilog and simulated using Modelsim 6.3f. FIR architectures of different combinations with respect to power, delay and area were generated using cadence 14.25, genus synthesis, and 180nm technology. On comparing with worst case, FIR architecture designed with Carry save multiplier using Fredkin gate and LCSA using Fredkin gate, in terms of area and number of cells occupied are good in performance. It was found that FIR architecture with Wallace multiplier using PFAG gate and Carry skip adder with PFAG gate has reduced area and cells by 63% and 54% respectively.
... A new reversible Half adder, Full Adder, Ripple carry Adders are being built using the proposed reversible logic gates. These gates satisfy the universality and reversibility conditions as a fundamental requirement for a reversible gate [16]. ...
In semiconductor industries power dissipation and the size of the computational devices are playing a major role. Size of a single transistor may limit the scaling of semiconductor devices. In turn, an alternative technology is needed for computational devices; one such technology is Reversible Logic. In this paper, a new set of reversible gates named as KMD Gates are proposed, they are capable of producing many logical functions compared to the conventionally available reversible gates. The proposed gates satisfy the reversibility and universality properties of reversible logic. In addition, these gates are having parity preservation, so they are fault-tolerant. A n-bit fault-tolerant reversible floating point division unit (FTRFPD) is designed in IEEE 754 single precision standard using the proposed fault-tolerant KMD reversible gates. This FTRFPD has parallel adder, latch, multiplexer, shift register, rounding and normalization register. All the functional blocks are fault-tolerant in nature as they are, they are constructed from the Fault-Tolerant Gates. The FTRFPD is capable of dividing two numbers using the non-restoring algorithm. Quantum Cellular Automata (QCA) is incorporated for validating the functionality of the reversible logic gates and division unit. The QCA based simulation results confirm that the designed unit is having reduction in Quantum Cost by 9.85%, in Delay by 29.63% and in Number of Gates by 33.54 % over the existing designs.
... Figure 7 is the RTL diagram of the 8 bit ALU which we have considered as a circuit under test and here we are implementing BIST architecture to test ALU. So here we are monitoring the incoming input vectors at the inputs of the ALU and verifying the output using response verifier 14 . ...
Background/objectives: Built in Self Test Architectures are used for the online or offline testing of the digital circuits and can be operated both in normal as well as test mode. So the objective is to test the circuit under test in online mode with less concurrent test latency and less area overhead. Methods/Statistical Analysis: In the case of normal mode the time required for testing becomes undesirable parameter so here we prefer offline testing method with concurrent approach which is also monitoring the window at the input by applying input vectors considering circuit under test as most important part of the processor which is arithmetic logic unit. Findings: The particular locations of the input vectors are stored in the latches which worked as the memory elements and this proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90. Application/Improvement: The proposed scheme is comparable with the same architecture, considering TPG as LFSR (Linear Feedback Shift Register) and counter.
Reversible circuits have gained a lot of attention lately because of its remarkable property of dissipating lesser power as compared to irreversible circuits due to the fact that they do not lose information. Because of continuing revolution in VLSI technology transistor count and thus power dissipation has increased to such an extent that it has put a limit on packing density and performance of the circuits. To overcome these limits reversible logic has came into picture and various reversible logic gates such as Feynman gate, Fredkin gate, Toffoli gate, Peres gate etc has already been designed in optical domain. Semiconductor optical amplifier (SOA) based mach-Zehnder interferometer (MZI) plays a promising role in this field of ultra fast all-optical information processing because of its advantages like high speed, low power, easy of fabrication and fast switching time. Thus various circuits designed by these basic gates has been analysed in terms of cost parameters and it was seen that optical cost and delay of digital circuits is more than desired, as a result performance of system is rendered. Thus new gates are designed by various researchers that focus on improving cost and thus performance of the system. Studying all these modified gates and the digital circuits implemented in literature, an idea of New All-optical universal reversible gate has been proposed which will further improve the performance of digital circuits. Applications of this gate include the design of full adder, half adder, multiplexer and various other combinational circuits and also 13 standard Boolean expressions can be implemented with improved cost. Simulation of this new gate is done using VPI Photonics software.
The objective is to design a new reversible logic gate for implementing parity checker and generator logic circuit and a magnitude comparator logic circuit with minimum computational time. Power dissipation seems to be a major drawback in all conventional irreversible logic circuits. As a solution to this, circuits can be constructed using reversible logic gates. According to the principle of reversible logic a new 3X3 gate named as SSG gate has been proposed. SSG gate has the ability to realize the following logic functions like XOR, NOR, OR, NOT, XNOR, AND and COPY. The proposed work can be implemented on a floating point subtractor and multiplier design. The proposed SSG gate is used to test the functionality of a even parity checker and generator circuit and it is compared with the circuit realized using existing Feynman gate. The comparative result shows that SSG parity checker and generator consumes 0.67 seconds less time compared with the existing gate. The comparative result of the 2-bit magnitude comparator designed using proposed SSG gate and with the existing reversible gate1 and Gate2 shows that the computation time for SSG gate comparator is reduced by 0.33 seconds with the existing reversible gate1 and gate2.
