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In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choos...
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In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid trade offs between power, delay and area, thus designers are required to choo...
A compressor is an applicable part that is broadly operated in VLSI circuits and its systems that take part in an important role in high-speed systems. This article computes that the new 7:3 compressor uses a 7-bit stacking approach using NOR gates that reduces power and delay as well as transistor count when compared to the existing one. In the ex...
This project report details the architecture of Serial Peripheral Interface (SPI) for a 32 byte Static Random Access Memory (SRAM) which was designed, simulated and tested using an 0.6um CMOS Technology. The project was accomplished using Tanner EDA tools to design, simulate and layout the circuits. The chip can be used as a low power consuming dev...
Citations
... Many researchers have strived to obtain substantial power savings. Singh et al. [3] have made a comparative study of various SRAM cell structures. They analysed the parameters such as power dissipation, output voltage, chip layout area and power efficiency. ...
The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %.
Evaluation of various SRAM cells on the basis of delay, power consumption and area occupied is investigated at 180 nanometer CMOS technology. Also, based on theoretic investigation, a new improved 7T SRAM cell with low-voltage, area efficient, less delay and low-power competence is proposed.
SRAM is the most common embedded memory for CMOS ICs. Due to CMOS technology scaling there is need to increase the on-die memory. As the integration density increases, power consumption has become the major concern for the today's SoC designs. However there is no universal rule to avoid tradeoffs between Power, Delay and Area. Thus appropriate techniques are chosen that satisfies the applications and product needs. This paper represents the simulation of different SRAM cell layouts and their comparative analysis at 120 nm technology and in the conclusion suggests an efficient SRAM memory cell in both the aspects: power consumption and speed. All the simulations has been carried out on a Microwind tool at 120 nm technology. SRAM is a basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit. It uses bistable latching circuitry made of transistors (MOSFETs) to store each bit and it works without refreshing. SRAM represents a large portion of the chip and is expected to increase in the future in both portable devices and high performance processors. To achieve longer battery life for portable applications low power SRAM is a necessity. Also it is important to design low power and fast responding SRAM since they are critical components in high performance processors. Solutions involving 7T, 8T, 9T, 10T SRAM cells have been explored for low power consumption. We will study different SRAM topologies and their layouts and perform analysis and simulation on the basis of different parameters such as power consumption, operating frequency, temperature and delay. 2. Literature Review of different SRAM topologies 2.1 6T SRAM CELL The schematic diagram of 6T SARM cell is as shown in figure 1a. During the read operation voltage is applied to the word line WL to turn ON the access transistors M5 and M6 and the memory cell discharges through either BL or BLB depending upon the stored data on nodes Q and QB. A sense amplifier converts the differential signal to a logic level output. During write operation voltage at WL is raised and BL's are forced to either VDD, overpowering the contents of the memory cell.[3] Minal Dubewar et al. / International Journal of Engineering Science and Technology (IJEST)
A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.
The advantages of simultaneous read and write operations for dual-port SRAM memory cells are well known. In this paper two configurations of dual-port 8-Transistor Differential (8T-D) and 7-Transistor Single End SRAM cells are presented. The benefits of power-delay product and power dissipation are verified. The goals of low power and high performance control of the full CMOS SRAM can be achieved. The main aim is to reduce the delay and power dissipation with better performance; compared to previous circuits are accomplished by changing the configuration of 8-transistor single-end SRAM cell. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results have confirmed that the proposed 8T-D and 7-Transistor SRAM cells can reduce propagation delay and power dissipation compared with the previous designs.
