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This paper presents an ultra-low-power receiver based on the injection-locked oscillator (ILO), which is compatible with multiple modulation schemes such as on-off keying (OOK), binary frequency-shift keying (BFSK), and differential binary phase-shift keying (DBPSK). The receiver has been fabricated in 0.18 μm CMOS technology and operates in the IS...
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... However, the RF front-end area of the receiver reached 5.91 mm 2 (180 nm), which does not satisfy the low-cost characteristics of the LPWAN. [4,5] reported two receivers of the ISM band, whose areas were 0.79 mm 2 (180nm) and 0.45 mm 2 (40nm) respectively; however, the sensitivity was only -82 dBm at 50 Kbps and -101.5 dBm at 31.25 Kbps, respectively. In addition, they have poor anti-interference performance and are not suitable for harsh industrial environments. ...
... The post-simulation results of the LNA are shown in Fig. 5. Compared with a 5.8 nH passive inductor (area 286 µm×287 µm), the proposed active inductor is up to 42 nH, which is only an area of 15 µm×72 µm, and the area of the LNA is reduced to 147 µm×66.58 µm, which is smaller than the area of the LNA reported in [4,9]. ...
In this work, a 0.43mm2 high-sensitivity low-intermediate-frequency (low-IF) receiver under 0.18 μm technology is reported for Industrial Scientific Medical (ISM) and Medical Implant Communications Service (MICS) band applications, which supports the 2ASK/GFSK demodulation mode. To reduce the area, a low noise amplifier (LNA) with an active inductor, a compact Gm-C filter, an AC current bleeding technique for controlling the receiver gain and, a ring-VCO LO PLL were used, without any passive inductors. The main methods for improving sensitivity are reducing the receiver noise figure (NF) and improving the signal-to-noise ratio for demodulation. Thus, the LNA adopts a two-stage 40 dB gain to suppress the NF of the subsequent stage. An automatic gain control (AGC) loop is used to control the receiver gain to overcome the large signal nonlinearity from the large LNA gains. Additionally, a Gm-C complex filter rejects image and blocks interference, improving the sensitivity to harsh environments. Under the CSMC 0.18 μm process, the die of the receiver is only 0.43 mm2 and covers 300-500 MHz, MICS and some ISM bands. The measurement results show that when the internal 2ASK demodulator is adopted, it has a -115 dBm sensitivity at 2 Kbps; and when the external GFSK digital baseband is adopted, it has a -121 dBm sensitivity at 2 Kbps. At 300 Kbps, only 6.5 mW of power is consumed. It is suitable for low-power wide-area network (LPWAN) applications.
... Table 1 compares the characteristics of the three embedded microprocessors. e above three embedded processors have a wide range of applications, and they are emphasized according to their respective characteristics [21]. PowerPC processors have strong floating-point performance and multimedia processing capabilities and are highly integrated; they are the first choice for high-end embedded applications, but their chips are more expensive and consume more power than ARM; therefore, mobile embedded devices such as mobile phones never use a PowerPC processor. ...
In order to explore how the Internet of Things implements a secure Internet of Things gateway technology, the author proposes a research on a secure Internet of Things gateway technology based on multicommunication methods. This method recommends key technical problems and solutions based on information represented by multiple communication methods and explores how the Internet of Things can realize the research of Internet of Things gateway technology. Research has shown that the security IoT gateway based on multiple communication methods is about 40% more efficient than the traditional method. By studying some exploratory guidance and suggestions for the development of the Internet of Things, it is found that there are still many problems to be solved before realizing the real Internet of Things environment.
... The amplitude unit β can be obtained by calculating the average signal power at the receiver and decoding it to the nearest amplitude codeword. The receiver implements an envelope detection [34]; therefore, certain active components can be omitted from the information decoder, such as low noise amplifier (LNA) and local oscillator (LO). Such features consume high power, making it very difficult to design self-sustaining SNs. ...
... The receiver implements envelope detection [34] to extract information. Envelope detector (ED) is considered one of the earliest and simplest signal detection devices. ...
Simultaneous wireless information and power transfer (SWIPT) presents a genuine opportunity toward achieving sustainable low-energy wireless devices. This paper introduces a receiver design for an energy harvesting sensor node (SN). The receiver is equipped with multiple radio frequency (RF) inputs. Furthermore, the receiver contains separate circuitries for information decoding (ID) and energy harvesting (EH) with dynamic power splitting (PS). The ID and EH circuits are connected to a power splitter that first combines all the RF inputs and then splits the power between the circuitries. Moreover, dynamic PS allows regulating the power split ratio between EH and ID circuitries. Consequently, the output of the EH circuit can be monitored and increased by adjusting the PS ratio. The proposed receiver design increases the harvestable energy by moving the ID into a separate circuitry. A voltage multiplier arranged in a Dickson scheme is used to level up the received voltage. At the transmitter side, the energy signal (ES) is sent through high power unmodulated continuous wave centered at the carrier frequency, while the information signal (IS) is sent via low power subcarriers around the carrier frequency. Such power allocation increases the harvestable power while reducing interference to external wireless networks. Moreover, different system measurements, including harvested energy from the received signal and data rates, are presented, where the split receiver scheme showed a significant improvement compared to the combined scheme in terms of harvestable power.
... Equations (4), (6), and (8) can realize a VM multifunction biquadratic filter structure, which consists of a non-inverting lossless integrator, an inverting lossless integrator and a proportional gain block, as shown in Fig. 1. (9) According to (9), the biquadratic ILPF and BPF transfer functions at different nodes can be obtained, respectively. ...
... Equations (4), (6), and (8) can realize a VM multifunction biquadratic filter structure, which consists of a non-inverting lossless integrator, an inverting lossless integrator and a proportional gain block, as shown in Fig. 1. (9) According to (9), the biquadratic ILPF and BPF transfer functions at different nodes can be obtained, respectively. ...
In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filter (BPF), low-pass filter (LPF), and inverting low-pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented. The synthesis structure of the VM biquadratic filter consists of a voltage proportional block and two voltage lossless integrators based on the use of current feedback operational amplifiers (CFOAs). It is demonstrated that the derived biquadratic filter structure can simultaneously realize VM HPF, BPF and ILPF transfer functions or VM BPF and LPF transfer functions at a high-input impedance terminal. The VM biquadratic filter can independently adjust the resonance angular frequency and quality factor. By slightly modifying the proposed biquadratic filter, a VM quadrature sinusoidal oscillator can be achieved. The proposed biquadratic filter and quadrature oscillator have been simulated by OrCAD PSpice and appropriate hardware has been implemented with AD844-type CFOAs. In order to reduce power consumption, reduce chip area, reduce costs, and improve system integration, integrated VM CFOA-based biquadratic filter circuits and quadrature oscillator circuits are very important. The proposed filter and quadrature oscillator have been further fabricated in 0.18 μm 1P6M CMOS process technology. The entire chip area is 0.974 mm2, including a filter chip cell and an oscillator chip cell. Under the supply voltage of ±0.9 V, the total power dissipation of the filter chip cell is 5.4 mW, and the figure-of-merit (FOM) of filter chip cell is 66.7%. The measured value of the third-order intermodulation distortion of the filter chip cell is -55.29 dBc and the third-order intercept point is 19.9 dBm. The measured phase noise of CFOA-based filter chip cell at 1 kHz offset is less than -99.76 dBc/Hz.
... Another important venue to improve the EE is to reduce the power consumption at the circuit level, e.g., through battery management techniques [7] or receiver architecture redesigns [8]. CMOS technology downscaling imposes huge challenges for RF designers, which need to meet severe system requirements while keeping power-consumption as low as possible. ...
Energy-efficiency is crucial for modern radio-frequency (RF) receivers dedicated to Internet of Things applications. Energy-efficiency enhancements could be achieved by lowering the power consumption of integrated circuits, using antenna diversity or even with an association of both strategies. This paper compares two wideband RF front-end architectures, based on conventional low-noise amplifiers (LNA) and low-noise transconductance amplifiers (LNTA) with N-path filters, operating with three transmission schemes: single antenna, antenna selection and singular value decomposition beamforming. Our results show that the energy-efficiency behavior varies depending on the required communication link conditions, distance between nodes and metrics from the front-end receivers. For short-range scenarios, LNA presents the best performance in terms of energy-efficiency mainly due to its very low power consumption. With the increasing of the communication distance, the very low noise figure provided by N-path LNTA-based architectures outperforms the power consumption issue, yielding higher energy-efficiency for all transmission schemes. In addition, the selected front-end architecture depends on the number of active antennas at the receiver. Hence, we can observe that low noise figure is more important with a few active antennas at the receiver, while low power consumption becomes more important when the number of active RF chains at the receiver increases.
In this paper, for the first time, a new method with closed-form analytical equations is presented to calculate the oscillation amplitude of fourth-order oscillators, such as quadrature oscillators. This method is actually based on the general form of the differential equations describing the structure of the fourth-order oscillators and finding a solution for the nonlinear differential equations governing this type of oscillators. The introduced method is a general method that is valid for all fourth-order oscillators and is also independent of the oscillation frequency. Using the proposed method, complex and time-consuming simulation tools will no longer be needed to calculate the oscillation amplitude in steady state. Moreover, the presented closed-form equations help the designers to understand the design compromises and design the oscillator for their specific and desired conditions. In addition, to evaluate the correctness of the presented equations, a comprehensive analysis of the oscillation amplitude of the quadrature oscillator in steady state is performed, and a closed-form equation is presented for the oscillation amplitude of the oscillator in the steady state, which is proposed for the first time in this paper. Comparison between the simulation results and theoretical computations confirms the validity of the proposed method.
