Fig 5 - uploaded by Praveen Choppala
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... first show the implementation of the proposed H-WT multiplier (we limit the demonstration to the H-WT case). The schematic of the GDI based 1-bit full adder and our H-WT multiplier using former are shown in Figures 5 and 6 respectively. For the multiplier implementation, the output waveforms are shown in Figure 7. ...
Citations
... Multipliers can be classified into several types, such as array multipliers, CSA multipliers, Wallace tree multipliers, Booth multipliers, etc. These multipliers are mostly implemented in the conventional complementary metal oxide semiconductor (CMOS) [8]. In contrast to CMOS logic, pass-transistor logic, which consists of pass transistors or pass gates, has been of great interest due to its advantage in the number of transistors. ...
The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.
... The FA and multiplier circuits (FMCs) being the primitive the blocks of multiply and accumulate circuit (MAC) determines the overall performance of the DSP system [1][2][3]. These FMCs consume a significant amount of power in any DSP-based system and hence it requires optimizing the performance of FMCs for targeted applications [4]. ...
... The referred works provide an insight limitation and propose a novelbased multiplier to further reduce power for VLSI Applications, the following are the most recent works mentioned in the overview. P. Choppala et al. [2] proposed a multiplier design that is area efficient, low power, and Full Swing Hybrid Multipliers. This research paper focuses on Gate Diffusion Input based hybrid FA of a 1-bit with only 14 transistors, within the standard array and WT multipliers. ...
