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In this paper, an area-optimized polyphase digital down converter (DDC) architecture is introduced, where the mixers can be completely merged into the polyphase decimation filter under certain conditions. We also introduce an interface architecture, called synchronizer, between the back-end of an extremely high-speed time interleaved ADC (TI-ADC) a...
Citations
... A digital front-end for direct-sampling receivers is implemented in [12], where digital mixers, cascaded integrator comb filters, Taylor-series polynomial interpolation filters (based on resampling for fractional decimation), and decimation-by-2 filters are employed. In [13], a digital down-converter with polyphase cascaded integrator comb filters is simulated to validate its compatibility with the time interleaved analog-to-digital converter. Parallel processing is employed in the channelization for an IEEE 802.11ac receiver in [14], which is implemented in software on a graphics processing unit. ...
... Similar to the aforementioned example design options 1, 2, and 3, various candidates in the architecture design space were evaluated before the final DFE architecture was proposed. A multitude of literatures deal with the DFE, including [2][3][4][5][6][7][8][9][11][12][13]17,[27][28][29][30], and many of them are based on the CIC filter, Farrow interpolator, and the FIR filter. However, most of them address only the simulated results and few of them explain the ASIC or FPGA implementation in detail. ...
A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).
... The path for the output 1 of NCO can be connected to input x and in the path of NCO output -1, binary negator is introduced. Polyphase filter is used to enhance the digital system block in terms of sampling rate [38,39]. Efficient multiplierless polyphase FIR filter is designed based on Distributed Arithmetic (DA) to diminish the hardware complexity. ...
This article presents a brief survey of Digital down Converter (DDC) architecture and its extensive applications. The distinctive feature of the DDC architecture is its frequency translation from real data signal at an intermediate frequency to a complex baseband signal at zero frequency. The architecture of DDC comprises of Numerically Controlled Oscillator (NCO) and decimation filters. The components of ultra efficient DDC architecture have been implemented in Field Programmable Gate Array (FPGA) device. This down converter provides high malleability, customizability and bearable cost. Due to its amenities, digital down converter was utterly studied and applied in many wireless communication technologies.
