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Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid–crystal display (...
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Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid–crystal display (...
Citations
A planarized copper gate thin-film transistor (TFT) using metal-induced laterally-crystallized polycrystalline‑silicon (poly-Si) was fabricated and characterized in this study. The planarized copper gate was able to structurally alleviate the drawbacks of copper and enhance stability to adapt in TFTs. Moreover, the surface of copper was systematically investigated by an electroplating process involving leveling additives such as thiourea and chloride in acidic sulphate-plating baths. These additives can improve surface morphology and ensure a smoother surface of the copper gate, which influence the electrical property of poly-Si TFT while reducing the surface roughness scattering effect. As the gate surface morphology was enhanced, the device exhibited superior electrical characteristics in field-effect mobility, on/off current ratio, and subthreshold slope.
We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p⁺ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm²/Vsec.
We report on a method to fabricate high-performance bottom-gate poly-Si (BGPS) thin-film transistors (TFTs) with a four-mask process via self-aligned (SA) NiSi
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seed-induced lateral crystallization (SILC). Previously, the BGPS TFT crystallized by SILC was reported to have high electrical performance with a simple process. However, this approach still requires an additional mask for lateral crystallization, making the process more complicated and expensive. In this letter, by using the SA-SILC method, only a few NiSi
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seeds reach the intrinsic Si surface through the side edges of the etch stopper and then crystallize the channel. This SA-SILC enables low metal contamination by a few seeds in the channel, shorter annealing time due to reduced length for SILC, and a simple four-mask process. The SA-SILC BGPS TFTs exhibited a steep subthreshold slope of 0.16 Vdecade
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, a high field-effect mobility of 230 cm
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V
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s
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, and kink-free output characteristics.
In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I
on
/I
off
ratio of ∼106.
