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This paper presents the design, fabrication, and comparison of different planar edge termination techniques on high-voltage 4H-SiC PiN diodes, including single- and double-junction termination extensions (JTE), floating guard rings, and a novel termination structure, the so-called "floating guard rings-assisted JTE." The influence of the anode meta...
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... considerable changes of the surface potential and create conductive surface paths on the low doped layer between rings. Thus, in order to make FGRs less sensitive to surface charges and to wider also the JTE range of the impurity concentration for obtaining high breakdown voltages we have proposed the "guard rings-assisted JTE" structure shown in Fig. 5. It is also an attractive structure because the guard rings are formed si- multaneously with the main junction, thus reducing processing steps compared to double ...
Citations
... Some in-plane edge termination techniques have been demonstrated for SiC power devices, which have a similar concept to that of Si power devices. The techniques include field plates [180,181], mesa structures [182], junction termination expansion (JTE) [183][184][185], floating field rings (FFR) [186,187], ramp structures [188,189], ion implantation, and hybrid solutions [37,[190][191][192][193]. Edge terminations are generally used at the device periphery so that it supports the maximum amount of the bulk breakdown value [194]. ...
Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.
... However, JTE needs the dopant activation process, which narrowed down the process window. Moreover, ion implantation induced field limiting ring was implemented to reduce the edge effect in the devices [21][22][23][24][25]. However, the formation of an mask for ion protection, need of multiple beam ion implantation, and extra procedures including high temperature ion activation makes the fabrication process of FLR complicated. ...
Power generation and its distribution are highly required to support the health-care, comfort, and transportation of next generation. Silicon-based power devices have reached their theoretical limit. Alternative solution is suggested by introduction of wide bandgap semiconductors, i.e., SiC, GaN, etc. Maturity in crystal quality and availability in the market makes SiC a promising candidate to adopt in fabrication of power devices. However, their full potential is inhibited by lack of efficient trench termination technique. This work reports trench terminated 4H-nSiC based Schottky barrier diode structure using Al2O3 as a dielctric material. ATLAS device simulator of Silvaco software is used to simulate the device structures. Various models like SRH and Auger recombination, Fermi Dirac, parallel and concentration field dependent mobility, incomplete ionization, Selberherr impact ionization, etc. have been included. Due to high potential and electric field crowding at edges of unterminated schottky barrier diodes, their is predicted as ~ 350 V. However, the potential and therefore the electric field at edges of SBD has been minimized by forming a trench at its edges. The trench in the designed structure is filled with SiO2, Polyimide and with Al2O3. The high permittivty of dielctric material filled in the trench leads to enhancement in breakdown voltage of the device to ~ 1875 V.
... 2) The GA-JTE-OR can shift the highest peak electric field from the edge of the main junction to the last guard ring. Additionally, both GA and OR structures can relieve the high electric field peak at the edge of the main junction and the main JTE structure by increasing the number of the peak electric field, which can enhance the device reliability [25,26]. ...
... sensitivity of BV for the low-dose case of the JTE structure [25,27]. In addition, the width and spacing of the outer rings, formed with the JTE structure, are 3 μm and 2 μm, respectively, which can reduce the sensitivity of BV for the high-dose case of the JTE structure [21,26]. ...
This paper reports the demonstration of a high performance 4H-SiC floating junction barrier Schottky (FJ_JBS) rectifier with a 30μm, 6×1015 cm-3-doped epitaxial layer. Extensive simulations have been performed to design, optimize and analyze the structure of the FJ_JBS rectifier. The fabricated FJ_JBS shows that breakdown voltage (BV) and differential Ron,sp are 3.4 kV, yielding the highest BV value reported for 4H-SiC FJ diodes, and 5.67 mΩ·cm2, respectively. Compared with the conventional JBS, the BV value of FJ_JBS increases by 33.3% and the Ron,sp only slightly rises by 6.2%. The corresponding Baliga figure-of-merit (BFOM) (4BV2/Ron-sp) of this FJ_JBS diode is 8.16 GW/cm2.
... In order to sustain the high voltage, the junction termination has to be designed to spread the electric field that naturally occurs at the edge of the termination. A plethora of papers present in the literature report on techniques that fulfill this task with a relatively high efficiency (>80%) [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35]. Another study on high-voltage bipolar diodes from SuperGrid has shown that an efficient peripheral protection is achieved by a mesa structure with a combination of junction termination extension (JTE) with JTE rings. ...
This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.
... However, it should be noted that a real device not only consists of active cells (for conducting current), but also edge termination (for protecting the device from premature breakdown). Conventionally, field limiting rings (FLR) [10], junction termination extension (JTE) and its modified forms [11]- [19] are used as the edge termination approaches. However, the FLR and JTE The ratio of termination area to total device area for 1200V devices with different current ratings operating at different current densities. ...
In this paper, the operation mechanism of the trench termination is investigated through 2D numeric simulation on Silvaco. It is found that in the trench termination, the electric field is terminated by the accumulated holes at the outer trench sidewall. In order to ensure a high termination breakdown voltage, the trench is refilled with a combination of SiO2 and polyimide (PI). Through various 2-D numerical simulations, the impact of structural parameters on breakdown voltage has been discussed, including trench depth, trench width, and sidewall tilt angle. 3D simulations are also conducted to investigate the effect of round corner radius on the device breakdown voltage and electric field in the dielectrics. Based on these results, the trench termination is designed and then fabricated along with a PiN diode. The measurement results show that a 14 lm wide trench is sufficient to terminate a voltage of 1750V (>96% of the ideal planar breakdown). Comparing with conventional FLR/JTE technology, this trench termination can significantly reduce the termination length by a factor of 4. As a result, the area efficiency is largely improved from 62% to around 90% for a 2A device conducting at 1000A/cm2. These results indicate that the SiC device price can be substantially lowered with such an area-efficient trench termination technology. Furthermore, the 168-hours high temperature reverse bias test under 1200V and 1750C shows the potential of this trench termination for long term reliable operation. Finally, UIS tests have been conducted on fabricated devices. Compared to commercial SiC JBS diodes with FLR, fabricated PiN diodes with trench termination show significant higher avalanche capability.
... [1][2][3][4][5][6][7][8] Therefore, development of vertical power devices using GaN substrates has attracted much attention. [9][10][11] In the fabrication of SiC vertical power devices such as PiN diodes [12][13][14] and doubleimplanted metal-oxide-semiconductor field-effect transistors [15][16][17] , ion implantation is generally employed to form edge termination structures, p-bodies and source regions. As for GaN, it has been reported that n-type GaN can be easily obtained by Si ion implantation followed by subsequent heat treatment at 1100°C. ...
... Finally, the design methodology in this work is as follows: -(i) SZJTE simulations with uniform doping concentration profiles are performed to obtain optimum doping concentration where maximum occurs, (ii) desired implant profiles are obtained, based on (i), and tailored using SRIM (Stopping and Range of Ions in Matter) [36], (iii) the implant profiles in (ii) are used to design and optimize the MZJTE structure. Fig. 1 shows the SZJTE structure, where the purpose of a JTE is to allow the spreading of equipotential lines emerging below the junction edge curvature toward the surface [37]. The effectiveness of the JTE lies on the charge available in it. ...
GaN is an attractive wide bandgap semiconductor for power applications, owing to its superior electrical properties such as high critical electric field and saturation drift velocity. Recent advancements in developing native GaN substrates has drawn attention towards exploring vertical GaN power diodes with high breakdown voltages (VBR). In practice, effective edge terminations techniques, such as junction termination extension (JTE) structures, play a crucial role in realizing high-voltage devices. Though certain challenges in fabricating GaN diodes, such as difficulty in forming p-type region, makes it difficult to realize edge termination, hence impeding the development and adoption of such devices. This work aims to address these challenges by presenting the design and methodology of forming multi-zone, counter-doped JTE structures in vertical GaN diodes, which attains close to theoretical breakdown voltage for a wide range of tolerance in implant dose variation. Extensive device simulations using experimental data and including the effects of surface charges and implant profiles, are performed to present realistic results. The results suggest that >80% of ideal VBR is achievable for a wide range of doping concentration (2.4 x 1017 cm-3) with a maximum VBR reaching 96% of the ideal value. This work serves as the first step towards leveraging the current challenges in the fabrication of GaN diodes, by proposing optimum design techniques for realizing vertical GaN diodes with high breakdown voltages.
... The results showed that, for 90% of the theoretical BV, a conventional SZ-JTE obtained a narrow JTE dose tolerance of 1.0 × 10 12 cm −2 . Therefore, many modified forms of JTE have been proposed to improve the sensitivity, such as guard ring-assisted JTE (GA-JTE) [15][16][17], double-zone JTE (DZ-JTE) [18,19], multiple-zone JTE (MZ-JTE) [20,21], etched JTE [22,23], counter-doped JTE (CD-JTE) [24], and mesa combined with JTEs [25,26]. Feng [14] also reported that the JTE dose tolerance (4.8 × 10 12 cm −2 ) in the conventional DZ-JTE was improved compared with the conventional SZ-JTE. ...
... Micromachines 2018, 9, x FOR PEER REVIEW 2 of 9 sensitivity, such as guard ring-assisted JTE (GA-JTE) [15][16][17], double-zone JTE (DZ-JTE) [18,19], multiple-zone JTE (MZ-JTE) [20,21], etched JTE [22,23], counter-doped JTE (CD-JTE) [24], and mesa combined with JTEs [25,26]. Feng [14] also reported that the JTE dose tolerance (4.8 × 10 12 cm −2 ) in the conventional DZ-JTE was improved compared with the conventional SZ-JTE. ...
In this paper, an edge termination structure, referred to as step-double-zone junction termination extension (Step-DZ-JTE), is proposed. Step-DZ-JTE further improves the distribution of the electric field (EF) by its own step shape. Step-DZ-JTE and other termination structures are investigated for comparison using numerical simulations. Step-DZ-JTE greatly reduces the sensitivity of breakdown voltage (BV) and surface charges (SC). For a 30-μm thick epi-layer, the optimized Step-DZ-JTE shows 90% of the theoretical BV with a wide tolerance of 12.2 × 1012 cm−2 to the JTE dose and 85% of the theoretical BV with an improved tolerance of 3.7 × 1012 cm−2 to the positive SC are obtained. Furthermore, when combined with the field plate technique, the performance of the Step-DZ-JTE is further improved.
... F OR high voltage power devices, the edge termination is vital to achieve the target breakdown voltage because the periphery of devices should be carefully protected from high electric field due to the junction curvature effect [1]. Conventionally, field limiting rings (FLR) [2], junction termination extension (JTE) and its modified forms [3]- [11], and Bevel termination [12]- [14] are used as the edge termination approaches. However, FLR termination consumes a significant amount of chip area. ...
Trench termination with SiO
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-encapsulated dielectric for 4H-SiC devices is proposed and experimentally demonstrated. The trench is mainly refilled with spin-on dielectric which is encapsulated with SiO2 to protect it from the high electric field in the trench. Such a trench termination is fabricated along with a high-voltage p-i-n diode. The fabricated device shows a repeatable breakdown voltage over 1750 V (96% of the ideal planar junction breakdown) with a termination length of 14 μm while the conventional trench termination has unrepeatable breakdown and requires over 30 μm termination length. Also, this termination length is less than ~1/4 of the dimension of a field limiting rings termination. Moreover, the fabrication process is robust with a large process window (Trench width ≥ 14 μm).
... The demonstration of p-type Ga 2 O 3 doping would allow the definition of Ga 2 O 3 p-n junction building blocks and therefore the equivalent of any conventional silicon-based devices could, in theory, be engineered; including MOSFETs, (complementary) CMOS logic or bipolar devices such as p-i-n diodes or insulator gate bipolar transistors (IGBT) [72]. P-type gate depletion is also a widely-applied strategy to make unipolar high mobility transistors normally-off in gallium nitride technology [73]. ...
