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Schematic cross section of (a) the SiC PiN diode with a p+ epitaxial layer and (b) SiC MOSFET. An internal pn diode (body diode) is formed in the MOSFET structure.
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We investigated the nucleation sites of expanded single Shockley-type stacking faults (1SSFs) in a silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) and demonstrated epitaxial layers designed for bipolar-degradation-free SiC MOSFETs. Since the sufficient hole density just below the basal plane dislocation (BPD)-thread...
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Citations
... [20][21][22][23][24][25][26] To reduce BPD densities in epilayers, techniques to convert BPDs to threading edge dislocations (TEDs) have been developed at the interfaces between the substrates and epilayers. [26][27][28][29] Although this BPD-TED conversion increases the device production rate, BPDs in the substrates still remain. BPDs in the substrates expand to 1SSFs when the minority carrier injection from the epitaxial layers is significant. ...
... BPDs in the substrates expand to 1SSFs when the minority carrier injection from the epitaxial layers is significant. [29][30][31][32][33][34][35] For example, in the MOSFETs with vertical structures based on SiC have p-n diode structures between the source and drain contacts, the p-n diodes temporarily turn on at the initial state of turn-off of the MOSFET during operation in electronic circuits. The turned-on p-n diodes induce the expansion of BPDs in the substrates to 1SSFs. ...
... The turned-on p-n diodes induce the expansion of BPDs in the substrates to 1SSFs. 21,27,29) Therefore, SiC MOSFETs with BPDs in the substrate gradually degrade during operation. Detecting this degradation before device operation is not easy because, the accurate location of BPDs in the substrates in the epiwafers cannot be observed using traditional inspection techniques. ...
Silicon carbide (SiC) is widely used in power semiconductor devices; however, basal plane dislocations (BPDs) degrade device performance, through a mechanism called bipolar degradation. Recently, we proposed that proton implantation could suppress BPD expansion by reducing BPD mobility. We considered three potential mechanisms: the hydrogen presence around BPDs, point defects induced by implantation, and carrier lifetime reduction. In this study, we discuss the mechanisms of proton implantation and its applicability to SiC power device production.
... The turn-on of p-n diodes induces a reliability issue due to bipolar degradation, which is caused by the expansion of basal plane dislocations (BPDs) to a single Shockley stacking fault (1SSF) [3,4]. The driving force of this expansion is the carrier recombination at the BPDs [3][4][5][6][7][8][9][10]. BPDs are typically present in SiC substrates but not in SiC epilayers because of the conversion of BPDs to threading edge dislocations (TEDs) at the interfaces between the substrates and epilayers [11][12][13]. ...
... With τ SRH = 10 ns, by inducing a recombination center with capture cross-sections for electrons and holes of 3.0 × 10 − 14 cm 2 and a concentration of 1.8 × 10 14 cm − 3 , the calculated distributions of the hole density for different current densities are shown in Fig. 1. If we assume the threshold hole density for the expansion of 1SSF to be 2 × 10 16 cm − 3 at the interface between the drift layer and the substrate [3,[5][6][7][8]15], the maximum current density is ~300 A/cm 2 , as shown in Fig. 1. Therefore, to fabricate devices with a current capacity of 300 A/cm 2 without 1SSF expansion, the drift layer should have τ SRH < 10 ns. ...
We analyzed the carrier lifetime in a drift layer of 1.2 kV-class SiC p-n diodes to suppress bipolar degradation. According to the device simulation results, the required carrier lifetime in the drift layer was estimated to be shorter than 10 ns with a current density of 300 A/cm² if the threshold hole density for the expansion of the stacking fault at the interface of the drift layer and substrate was 2 × 10¹⁶ cm⁻³. Numerical analysis revealed that to ensure a carrier lifetime shorter than 10 ns, the 1/e² lifetime obtained by microwave photoconductivity decay (μ-PCD) measurements should be shorter than 7.2 ns. Experimental μ-PCD measurements showed that 1/e² lifetimes obtained from the as-received epiwafer were much longer than 7.2 ns, and even after H⁺ implantation, high-temperature annealing, or electron irradiation, 1/e² lifetimes were still long. Therefore, carrier lifetime control in the drift layer is not sufficient to suppress bipolar degradation, and a combination of carrier lifetime control with other methods is necessary for the fabrication of 1.2 kV-class SiC p-n diodes for the complete suppression of bipolar degradation at a current capacity of 300 A/cm².
We are currently developing an inspection system that will provide a low-cost means of screening prior to shipment by fully visualizing latent 1SSF (single Shockley stacking fault) defects originating from basal plane dislocations (BPDs) that cannot be detected by current defect inspection systems. The system will capture not only the defects that expand into right triangles under relatively low-level forward bias, but also the defects that expand into more serious bar-shaped 1SSFs under relatively high-level forward bias, with a particular focus on capturing TED (threading edge dislocation)-converted BPD at or below the buffer layer/substrate interface. Since these defects are known to cause forward voltage degradation during device operation, so-called "burn-in" (accelerated current stress) screening operation is currently utilized in some device manufacturers to avoid the shipping of the defective devices, but it is very time-consuming process which raises a total cost of production. The system we are developing, which can significantly reduce the screening time, has the potential to replace the "burn-in" operation.
4H-SiC has been commercialized as a material for power semiconductor devices. However, the long-term reliability of 4H-SiC devices is a barrier to their widespread application, and the most important reliability issue in 4H-SiC devices is bipolar degradation. This degradation is caused by the expansion of single Shockley stacking-faults (1SSFs) from basal plane dislocations in the 4H-SiC crystal. Here, we present a method for suppressing the 1SSF expansion by proton implantation on a 4H-SiC epitaxial wafer. PiN diodes fabricated on a proton-implanted wafer show current–voltage characteristics similar to those of PiN diodes without proton implantation. In contrast, the expansion of 1SSFs is effectively suppressed in PiN diodes with proton implantation. Therefore, proton implantation into 4H-SiC epitaxial wafers is an effective method for suppressing bipolar degradation in 4H-SiC power-semiconductor devices while maintaining device performance. This result contributes to the development of highly reliable 4H-SiC devices.
4H-SiC has been commercialized as a material for power semiconductor devices. However, the long-term reliability of 4H-SiC devices is a barrier to their widespread application, and the most important reliability issue in 4H-SiC devices is bipolar degradation. This degradation is caused by the expansion of single Shockley stacking faults (1SSFs) from basal plane dislocations in the 4H-SiC crystal. Here, we present a method for suppressing the 1SSF expansion by proton implantation on a 4H-SiC epitaxial wafer. PiN diodes fabricated on a proton-implanted wafer show current–voltage characteristics similar to those of PiN diodes without proton implantation. In contrast, the expansion of 1SSFs is effectively suppressed in PiN diodes with proton implantation. Therefore, proton implantation into 4H-SiC epitaxial wafers is an effective method for suppressing bipolar degradation in 4H-SiC power-semiconductor devices while maintaining device performance. This result contributes to the development of highly reliable 4H-SiC devices.
