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3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process whic...
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... alternative solution consists of 3D structures based on a well-known dielectric with good electrical properties. In our case, 3D capacitors are integrated between two metallic levels ( Figure 1), during via definition and filling. Electrodes are done with TiN and the dielectric is a PECVD Si 3 N 4 , which presents better dielectric relaxation properties than Ta 2 O 5 one [2]. ...
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... One of the major challenges for analog and RF technologies is to provide passive components like MIM capacitors with high surface capacitance while keeping good voltage linearity and good reliability. To deal with high density MIM capacitor, a three-dimensional (3D) architecture is integrated among copper interconnects between 2 metallic levels during via definition and filling [2]. The figure Ashows the cross section of MIM structure after CMP. ...
... Figure B: MIM process flow description -1 -MIM definition (lithography and dry etch) -2 -Trench filling with electrodes, dielectric and copper -3 -Structure planarization with CMP [2] We can notice that bottom and top electrodes can be TaN/Ta or TiN/TaN/Ta or WNC/TaN/Ta layers. Indeed, the electrode materials for 3D MIM in copper back-end have: -To prevent copper diffusion to keep the dielectric integrity -To be low resistive for limiting access resistance -To have high work function for low leakage current level -To be CMP compatible -To have good adhesion on copper and dielectric -To have good uniformity. ...
To deal with the continuous increase of chip component density, high density Metal-Insulator-Metal (MM) capacitors are required for analog and Radio Frequency (RF) applications [1]. Instead of introducing high-k materials Ta 2O5, HfO2...), an alternative is to develop a three-dimensional (3D) architecture providing higher developed area and to introduce electrode material with high work function for low leakage current level like WN or WNC. These materials will change the CMP requirements in copper back-end integration. In this paper, we will present the integration flow of 3D capacitor with WNC top electrode and then discuss on material CMP strategy, which gives good performances on 3D MIM capacitor.
