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Schematic and behavior of MRL gates. (a) The schematic of an OR logic gate, and (b) an AND logic gate. Both logic gates consists of two memristive devices where the polarity of the memristive devices is the only structural difference. The behavior of (c) an OR logic gate, and (d) an AND logic gate when VIN1 = '1' and VIN2 = '0'. The current flows from VIN1 to VIN2 and the resistance of the memristive devices changes for the (e) OR, and (f) AND logic gates. The continuous and dashed lines are, respectively, the resistance of R1 and R2.
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Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are ad...
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... In the pursuit of memristive digital logic circuits, a variety of implementation methods have been proposed, such as IMPLY (material implication) [8], MRL (memristor ratioed logic) [9] and MAGIC (memristoraided logic) [10] for binary logic. Studies have also proved that replacing CMOS gates with memristors can effectively reduce circuit area and power consumption. ...
In this paper, a high-density programmable logic array based on a ternary memristor crossbar array is designed. Based on the three-valued state characteristics of the ternary memristor, we implement the ternary OR logic gate and a standard ternary inverter to demonstrate the application of this proposed crossbar by using reconfigurable and programmable connections of the memristor cells in the array. Subsequently, on the basis of these logic gates, ternary NAND gates, NOR gates, XOR gates and XNOR gates are further realized. The above-mentioned logic gates all use memristance as the logic state variable. Finally, we verified the functionality of the programmable gate array based on the proposed ternary memristor crossbar through SPICE simulation and gave the power consumption of each circuit under different input conditions. Compared with existing ternary memristor cross array circuits, our circuit has the advantages of low power consumption and high integration.
... Ox RRAM characterization data is acquired using the compact Verilog-A code of the VTEAM [23] model, which shows the non-linearity property required with an adjustable threshold voltage. Among the available memristive logic families, CMOS compatible Memristor Ratioed Logic (MRL) [24] is used. ...
In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area.
... TaO xbased devices show potential for high-density non-volatile memory due to their speed, energy efficiency, and endurance [6,7]. Memristors also hold promise in storage-computing applications like digital logic [8,9,10] and artificial synapses [11,12]. By integrating storage and computing, TaO x -based memristors can overcome traditional transistor memory limitations [13], offering a new approach in the post-Moore era. ...
... It was used to design a memristor-based logic circuit in Cadence Virtuoso, being more efficient and suitable for circuit-level simulations compared to previous models [18,19]. The TaO x model allowed constructing a XOR gate based on memristor ratioed logic (MRL) [8] and further extended to a 1-bit full adder circuit, showcasing its universality. Designed logic circuits offer advantages over traditional CMOS logic circuits, including lower power consumption, higher expansibility, and higher integration density. ...
... State logic assigns logical values based on memristor resistance, where the high resistance state (R off ) corresponds to "0" and the low resistance state (R on ) corresponds to "1." Key state logic circuits include memristor-based material implication (IMPLY) logic [28] and memristor-aided logic (MAGIC) [9,10]. In contrast, level logic uses voltage levels, with high voltage (V high ) representing "1" and low voltage (V low ) representing "0." Logic scenarios based on voltage levels often involve memristor ratio logic (MRL) [8]. IMPLY and MAGIC logic circuits require external stimuli to continually adjust memristor resistance for logic output. ...
The traditional complementary metal oxide semiconductor (CMOS) process technology is approaching its limits due to the continuous shrinking of current semiconductor processes, which has implications for all aspects including device size, performance, power consumption, etc. These aspects also create bottlenecks in traditional Von Neumann computing architecture. As a new type of device that integrates computing and storage functions, the memristor is thus one of the candidates for breaking the mold in the post-Moore era. Here, we study TaOx-based memristors from a simulation point of view, which is one of the best-performing memristors available. Firstly, we combine the quantum point contact (QPC) model and thermal dissolution mechanism to build a compact Verilog-A model of the TaOx memristor, which is in good agreement with the experimental characterization data of TaOx devices. Then, we apply the compact model of TaOx memristor to logic circuits, and construct a new XOR gate based on the principle of memristor ratio logic (MRL), which can be used to cascade multiple logic gates. Furthermore, we extend these simple logic gates to construct a 1-bit full adder. The results show that the circuit described in this work is much improved in terms of power consumption and integration density compared to conventional CMOS circuits.
... A novel CMOS-like gate is presented in [4], by replacing pMOS-and nMOS-transistors with anti-polarized memristive devices. Utilizing the voltage division effect between two series-connected memristive devices the memristor ratioed logic (MRL) was developed by Kvatinsky as well [5]. Moreover, non-stateful binary logic concepts have been developed where the inputs are encoded as voltages applied to the two terminals of one memristive device [6]. ...
... Numerous approaches have been put out in the literature to implement logic operations utilizing memristors, including Memristive Threshold Logic [17], [18], Memristive Rationed Logic [19], and Memristor-CMOS Hybrid Logic [20]. Only the IMPLY gate and the MAGIC NOR/NOT gate can be mapped to the memristor crossbar array. ...
Performance degradation and higher power dissipation for data-intensive applications are common in von Neumann computers. This is due to data transfer between the memory and processor. Non-von Neumann architecture addresses this issue by performing computations within the memory, that is, in-memory computing. The non-volatile memory can be built using an alternative building block called a memristor. Logical NOT and NOR gates can be realized on memristor crossbars. This allows to perform arithmetic and logic operations within the memory. An architectural support for a constant time in-memory comparison has been introduced. This adds FILL and MCMP instructions to the instruction set. Four basic set operations are implemented using the instruction set. In-memory union, cartesian product, transitive closure, and power set generation achieve an average energy reduction of 168×, 249×, 134×, and 264×, respectively. However, for higher input sizes, CPU-based union, cartesian product, and transitive closure perform better by an average of 1.58×, 1.23×, and 2.07×, respectively. In-memory power set generation achieves an average speed-up of 1.14×.
... In the pursuit of memristive digital logic circuits, a variety of implementation methods have been proposed, such as IMPLY (Material Implication) [8], MRL (Memristor Ratioed Logic) [9], and MAGIC (Memristor-Aided Logic) [10] for binary logic. Studies have also proved that replacing CM-OS gates with memristors can effectively reduce circuit area and power consumption. ...
... This design was completed using MRL--a hybrid CMOS-memristive logic family [13].In this logic family, the high level (VH) represents logic '1', and the low level (VL) represents logic '0'. . OR gate [12]. ...
Integrated circuits have advanced quickly alongside the semiconductor industry's tremendous growth. The primary design considerations for each circuit in a VLSI data path are minimization of area and power consumption. As a very important logic unit in the integrated circuit, reducing the flip-flop's power consumption is of great significance for improving the performance of the whole circuit. There are many ways to reduce the power consumption of the flip-flop. This paper reviews several new low-power flip-flop designs using methods to improve the logic structure of flip-flops and their logic gates, including a reversible flip-flop design with reversible gates, a flip-flop design with memristors, and a sense amplifier-based flip-flop. The analysis shows that all three options for improving the logic gate can reduce the power consumption of the flip-flops and also have a positive effect on reducing the size of the device.
... Memristor is modeled as a Bipolar switching device in this study and generalized as follows. When a voltage is applied on one polarity SETs the device, then it RESETs in the other direction as shown in Fig. 3 [19]. This logic is used to simulate the circuits. ...
... Memristor ratioed logic (MRL) [19] based AND and OR gates were designed as shown in Fig. 6 (a&b), further Universal gates, NAND and NOR, were designed using the symbols created in cadence as shown in Fig. 7. These universal gates are used to build high-level circuits. ...
... As the devices scale down, memristors provide a new approach to continue Moore's law and overcome the bottlenecks of a conventional computer with a von Neumann architecture. Memristors have many advantages, such as nanoscale size, simple structure, extremely fast working speed, low power dissipation compared to traditional devices, and compatibility with traditional CMOS processes [3][4][5]. Applications of memristors include non-volatile memories [6], artificial neural networks [7][8][9][10][11], digital logic operations [12], chaotic circuits, and other fields [13][14][15]. The future development and applications of memristors are reviewed in [16]. ...
... Kvatinsky first proposed logic circuits constructed using memristor CMOS hybrids in [3]. The AND and OR gates are composed of two serial memristors with identical and opposite polarity, respectively. ...
Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.
... According to the components, the logic circuits based on memristors can be divided into two categories. One is the hybrid CMOS-memristor-based logic, which mixes the CMOS logic and memristive logic, such as the memristor ratioed logic (MRL) [17] and memristorbased threshold logic gates(TLGs) [18]. The other one is memristor-only logic, which includes stateful logic and sequential logic. ...
Memristor is one of the most promising emerging technologies to solve the von Neumann bottleneck problem due to its non-volatile and binary characteristics. This paper studies the design method of high-efficiency logic circuit based on memristor. First, a multiple-input-multiple-output (MIMO) logic circuit design scheme based on IMPLY and AND logic is proposed, which can derive multiple new efficient logic operation methods and complete complex logic with fewer steps and memristors. Second, in order to perform rapid interactive operations between different rows, an alternating crossbar array structure is designed which can quickly complete cross-row logic operations. Finally, a high-efficient full adder (FA) based on MIMO logic and alternating crossbar array is proposed. To accomplish 32-bit add operation, the proposed FA needs 160 memristors and only 41 steps. Compared with the state of art FA, our work has faster execution speed and fewer memristors.
