Fig 8 - available via license: CC BY-NC-ND
Content may be subject to copyright.
Source publication
The avionics working environment is bad, easy to accelerate aging of circuits. Circuit aging is one of the important factors that influence the reliability of avionics, so circuit aging testing is of great significance to improve the reliability of avionics. As continuing aging would degrade circuit performance, aging can be monitored through preci...
Context in source publication
Context 1
... more functions. When pin TC receives a high level, it works as a D flip-flop. On the contrary, it works in the pattern of the scanning mode, and the data on pin SD would be scanned. CK is the clock input. Q and Q are two opposite outputs, respectively. In order to control and observe the state of each SFF, the scan chain is practical, as shown in Fig. 8. The SCA-NIN and SCANOUT define the input and output of a scan chain, respectively, and the output of each SFF is connected to the scanning input (SD) of the ...
Citations
... These structures can respond to fast delay changes but are activated only after the path delay change exceeds a threshold, so they can only infer circuit delays in a coarse-grained manner. Another in situ method is ring-oscillator-based measurements, which are commonly used in circuit delay monitoring and called path-based ring oscillators (Path-ROs) [16][17][18][19][20][21][22][23]. In this method, the critical path itself is configured as an RO using some measurement control structures (MCs) by reusing the existing design for test (DFT) on-chip. ...
... The existing Path-ROs in [18][19][20][21] insert an MUX as an MC in each PUM to configure the path as a Path-RO. Based on this, some studies [18,19] add the hardware-based calibration function by redesigning DFF along the critical paths using more MUXs. ...
... The existing Path-ROs in [18][19][20][21] insert an MUX as an MC in each PUM to configure the path as a Path-RO. Based on this, some studies [18,19] add the hardware-based calibration function by redesigning DFF along the critical paths using more MUXs. One study [21] provides adjustable accuracy for the measurement result through a reconfigurable inverters chain lying between the Path-ROs, and the latest literature [22,23] redesigned the MUX for the auto-enable process to reduce the wire length of the control signals. ...
Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, which is more conducive to engineering change order (ECO). Measurement simulation experiments were performed on representative critical paths of the ISCAS’89 s298 and ITC’99 b15 benchmark circuits. The experimental results show that, in comparison with the existing architectures, the Bpath-RO delay measurement scheme improves the circuit performance by an average of 13.81% (s298) and 3.47% (b15) and reduces the hardware overhead by up to 70% for each path.
... Some of the researches focus on hardware resource optimization [4][5][6], while some other on speed optimization [7][8][9] and some other on power consumption optimization [10][11][12][13]. A very few works on built-in-self-test (BIST) has reported in literature [14][15][16][17][18]. Some of them focus on-chip test pattern generation on detecting circuit aging [14][15][16], and some other structures detect Trojans [17,18]. ...
... A very few works on built-in-self-test (BIST) has reported in literature [14][15][16][17][18]. Some of them focus on-chip test pattern generation on detecting circuit aging [14][15][16], and some other structures detect Trojans [17,18]. The testability and hardware Trojans are two major concerns that make the AES chip complex and vulnerable. ...
... The detection threshold in (2) and the CPR in (5) can be rewritten as in (13) and (14) respectively by putting (r j,intra − r i,intra ) = r ji,intra . ...
Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform’s reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.
... However, for designing ASIC or any complex chip, Design for Testability (DFT) is a prime concern because testing a VLSI chip using Automatic Test Equipment (ATE) is highly complex, time-consuming as well as expensive [23,24]. To deal with the testing problem at the chip level, incorporating Built-in Self-Test (BIST) capability inside a chip is a widely accepted approach [25][26][27][28][29][30] and it is a norm of this day in the VLSI industry. BIST is a mode of operation of a chip other than its normal mode, where when a chip is switched to this mode, it performs its test by itself. ...
This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.
... Memory density and area are increasing day by day in embedded memory cores and SOCs. Thus on-chip memory yield defines the major portion of chip yield which can be improved with memory diagnosis and failure analysis (FA) methodologies [2]. The March tests are very convenient and efficient for testing RAM and are normally used with small test sizes [3]. ...
The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient algorithm a hybrid memory testing algorithm is presented. To overcome those drawbacks, pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm. By introducing the Pipelining approach, majorly path delays are reducing. The proposed architecture designed and verified using Xilinx ISE environment under various testing methods with respect to the different category of memories. The simulation and synthesis results shows that the proposed method shows the enhanced performance with the hardware resource utilization and delay consumption compared to the conventional approaches.
The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient algorithm a hybrid memory testing algorithm is presented. To overcome those drawbacks, Pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm. By introducing the Pipelining approach, majorly path delays are reducing. The proposed architecture designed and verified using Xilinx ISE environment under various testing methods with respect to the different category of memories. The simulation and synthesis results shows that the proposed method shows the enhanced performance with the hardware resource utilization and delay consumption compared to the conventional approaches
As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.
One of the most important issues in deep nanoscale regime CMOS circuits is related to the time-dependent performance degradation caused by negative bias temperature instability (NBTI). The integration of online aging sensor is becoming attractive methodologies in monitoring performance degradation of circuit. The sensor can generate a warning signal, early warning of the occurrence of aging faults, to avoid unnecessary losses. To accurately capture the aging fault, a real-time aging sensor is proposed with mirror extraction setup and hold (SH) time method. The proposed aging sensor, which is on the basis of the standard flip-flop (FF), consists of an additional edge detector circuit, a detection window generator circuit, and an output warning circuit. Having the adaptive characteristic of detection window, aging sensor is able to adjust its NBTI effects and improve the stability. Also, the sensing network supports multiple paths online detection from many SH sensors for IP chip applications. Finally, the Camellia IP layout is inserted with 20 aging sensors and is implemented under 65-nm CMOS process. Experimental results demonstrate the effectiveness of area, power, and performance overheads. Compared with other state of the art, hardware efficiency is increased by 46%, and energy is decreased by about 37%.
