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Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early TRL....
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... IV. In Section V, the HISM is applied to a practical example representing a 5 MVA battery energy storage system (BESS) power conversion equipment [22] with an SDC in the laboratory. The theoretical analysis is, then, validated by comparing offline digital simulations and PHIL results in Section VI followed by the conclusion in Section VII. Fig. 1 shows the single line diagram of the PHIL setup. On the left-side, the dc-grid emulator is connected to the dc link of the converter. The capacitor at the dc link is denoted by C dc and the voltage across this capacitor is named V dc . The current flowing into the dc-side of the PEC is named I dc . The dc-grid emulator operates as a ...
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... scaled when the real-life converter is expected to regulate the dc-voltage through an active current loop. In such cases, a proper modeling of interactions between the converter controller and the dc-capacitance is critical. However, H is not as critical when the FSC dc-link is fed by an active source like a battery as in the scenario depicted in Fig. ...
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... grid ancillary services such as frequency and voltage support, peak shaving of distributed generation, etc. It is impractical to invest on deploying the entire power conversion system in the laboratory especially for studies related to PWM techniques, harmonic penetration into the grid, and impact on power quality. The PHIL system presented in Fig. 1 can easily be made to represent a practical BESS. This is done by controlling the dc and ac emulators to respond as a battery bank and as an electric grid, respectively, and by physically representing the FSC with the SDC, as shown in Fig. ...
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... techniques, harmonic penetration into the grid, and impact on power quality. The PHIL system presented in Fig. 1 can easily be made to represent a practical BESS. This is done by controlling the dc and ac emulators to respond as a battery bank and as an electric grid, respectively, and by physically representing the FSC with the SDC, as shown in Fig. ...
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... the SDC are performed at the National Smart Grid Laboratory, see Fig. 4. An oscilloscope with a bandwidth of 20 MHz, no extra filtering nor smoothing, is employed for measuring two phases of the phase-to-ground voltage across the shunt capacitor and two phases of the current across the converter reactor which are indicated by V ac and I ac in Fig. 1, respectively. The measurements, scaled up to FSC levels, are presented in Figs. 5a and 5c. The active and reactive power (Figs. 5b and 5d) are calculated from the scaled up voltages and currents. They represent the power flow at the point indicated by P, Q in Fig. 1. A moving average filter with window equal to 20 ms is applied to the ...
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... the current across the converter reactor which are indicated by V ac and I ac in Fig. 1, respectively. The measurements, scaled up to FSC levels, are presented in Figs. 5a and 5c. The active and reactive power (Figs. 5b and 5d) are calculated from the scaled up voltages and currents. They represent the power flow at the point indicated by P, Q in Fig. 1. A moving average filter with window equal to 20 ms is applied to the power measurements. The voltages, active power, and reactive power, obtained with Case 1 (green) and Case 2 (red) are similar to the ones obtained with a computer simulation (black) of the FSC. However, the switching ripple in the current across L ac for Case 2 is ...
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p>Aiming to investigate the possible interactions between smart grid components during transient events, an advanced hardware-in-the-loop testing chain for the validation of novel smart grid solutions is proposed in this paper. The testing chain is directed towards both academic and industrial HIL users, e.g., relay manufacturers, power electronics...
p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on September 2023.
Abstract: Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simula...
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p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on September 2023.
Abstract: Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simula...
Citations
... A compromise between reducing losses and matching reactance and capacitance values in pu has to be made for a scaled-down PHIL test. This topic is addressed in more detail in [70]. ...
This paper examines the use of interconnected synchronous system requirements for frequency containment reserves (FCR) on isolated industrial grids that use turbogenerators as main source of energy, have high penetration of wind energy, are equipped with energy storage, and have a high level of constant power loads coupled by power electronic converters. Leveraging on the recent Nordic requirements for reserves in islanded operation (FCR
$_{\rm {I}}$
), we propose an expansion that allows prioritizing among various reserve providers accounting for different isolated grid conditions. The study case of a complex, isolated industrial grid is selected to test this approach. The stability of this grid is evaluated via eigenvalues and participation factors considering the detrimental effects of constant power loads. It is demonstrated that, by prioritizing the reserve allocation to the faster converter-interfaced storage devices and loads, the overall stability is increased in addition to allowing the turbogenerators to operate at a more constant load. The results are supported by computer simulations of the complex isolated grid in DIgSILENT PowerFactory and by laboratory power-hardware-in-the-loop tests which compare the performance of the proposed concept with the industry consolidated droop control. The computer simulation models developed for this paper are made publicly available for reproducibility purposes.
... For the SDC, despite the maximum voltage on the dc link being 700 V, the operating dc link is decided by the ac/dc ratio of the FSC that it will represent in PHIL tests as given in (16).The superscript f sc denotes quantities related to the FSC and the superscript sdc denotes quantities of the SDC. If this ratio is not maintained, the SDC converter harmonic spectrum resulting from PWM switching will differ from the FSC, leading to higher converter voltage and current distortion when scaled to represent the FSC [11]. Based on these assumptions, the dc link voltage of the SDC is calculated as in (17) and the same is used for generating the power capability curve in Fig. 3b. ...
... unit capability curve of the SDC and the FSC are plotted together as shown in Fig. 7. It is important to remember here that per unit capability curves are obtained without violating (17), which is the fundamental step in achieving the harmonic invariance with scaling of an SDC to an FSC, as mentioned in [11]. In Fig. 7a, per unit capability curves of an FSC and an SDC are plotted at V s = 1.0 pu. ...
... As a starting step, the MATLAB script acquires all the required design parameters of the converter, transformer and LCL filter (for both FSC and SDC). As learned from the previous work [11], the dc link of the SDC in the second step should be selected as (16) for harmonic invariant scaling. Following this, the method plots the per unit power capability curves of both the FSC and the SDC (plotted on the same x and y axes). ...
Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simulator, thus enabling the study of real-time interactions of power electronics with large power systems. However, assembling an accurate scaled-down replica of an FSC with off-the-shelf laboratory SDCs is practically impossible due to a mismatch in per unit losses, as well as in the impedance of the L/LC/LCL filter. Consequently, the scaled-up power flow capability of SDCs differs from FSCs, restricting emulation to smaller regions of the four quadrants than those corresponding to the FSCs nominal active and reactive capacity. These PHIL test beds cannot be used to emulate FSCs demanding bidirectional active and reactive power flow. Any scaling method on SDCs, emulating the entire operation of FSCs, demands underutilisation of SDCs, reducing the advantages of PHIL tests. This paper, therefore, proposes a physics-informed scaling method that exploits power capability curves to emulate FSCs in all four quadrants of operation. This method is independent of SDC topology, filter type, and interfacing methods. A visual identification of the semiconductor device constraints bounding the emulation is also presented, utilizing the physics of converter control. A theoretical analysis of the proposed method is presented, followed by validation with MATLAB simulations and experimental tests using a 50kVA SDC.
... For the SDC, despite the maximum voltage on the dc link being 700 V, the operating dc link is decided by the ac/dc ratio of the FSC that it will represent in PHIL tests as given in (16). If this ratio is not maintained, the SDC converter harmonic spectrum resulting from PWM switching will differ from the FSC, leading to higher converter voltage and current distortion when scaled to represent the FSC [11]. Based on these assumptions, the dc link voltage of the SDC is calculated as in (17) and the same is used for generating the power capability curve in Fig. 2b. ...
... The problem is better viewed if the per unit capability curve of the SDC and the FSC are plotted together as shown in Fig. 6. It is important to remember here that per unit capability curves are obtained without violating (17), which is the fundamental step in achieving the harmonic invariance with scaling of an SDC to an FSC, as mentioned in [11]. In Fig. 6a, per unit capability curves of an FSC and an SDC are plotted at V s = 1.0 pu. ...
... As a starting step, the MATLAB script acquires all the required design parameters of the converter, transformer and LCL filter (for both FSC and SDC). As learned from the previous work [11], the dc link of the SDC in the second step should be selected as (16) for harmonic invariant scaling. Following this, the method plots the per unit power capability curves of both the FSC and the SDC (plotted on the same x and y axis). ...
p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on September 2023.
Abstract: Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simulator, thus enabling the study of real-time interactions of power electronics with large power systems. However, assembling an accurate scaled-down replica of an FSC with off-the-shelf laboratory SDCs is practically impossible due to a mismatch in per unit losses, as well as in the impedance of the L/LC/LCL filter. Consequently, the scaled-up power flow capability of SDCs differs from FSCs, restricting emulation to smaller regions of the four quadrants than those corresponding to the FSCs nominal active and reactive capacity. These PHIL test beds cannot be used to emulate FSCs demanding bidirectional active and reactive power flow. Any scaling method on SDCs, emulating the entire operation of FSCs, demands underutilisation of SDCs, reducing the advantages of PHIL tests. This paper, therefore, proposes a physics-informed scaling method that exploits power capability curves to emulate FSCs in all four quadrants of operation. This method is independent of SDC topology, filter type, and interfacing methods. A visual identification of the semiconductor device constraints bounding the emulation is also presented, utilizing the physics of converter control. A theoretical analysis of the proposed method is presented, followed by validation with MATLAB simulations and experimental tests using a 50 kVA SDC.</p
... For the SDC, despite the maximum voltage on the dc link being 700 V, the operating dc link is decided by the ac/dc ratio of the FSC that it will represent in PHIL tests as given in (16). If this ratio is not maintained, the SDC converter harmonic spectrum resulting from PWM switching will differ from the FSC, leading to higher converter voltage and current distortion when scaled to represent the FSC [11]. Based on these assumptions, the dc link voltage of the SDC is calculated as in (17) and the same is used for generating the power capability curve in Fig. 2b. ...
... The problem is better viewed if the per unit capability curve of the SDC and the FSC are plotted together as shown in Fig. 6. It is important to remember here that per unit capability curves are obtained without violating (17), which is the fundamental step in achieving the harmonic invariance with scaling of an SDC to an FSC, as mentioned in [11]. In Fig. 6a, per unit capability curves of an FSC and an SDC are plotted at V s = 1.0 pu. ...
... As a starting step, the MATLAB script acquires all the required design parameters of the converter, transformer and LCL filter (for both FSC and SDC). As learned from the previous work [11], the dc link of the SDC in the second step should be selected as (16) for harmonic invariant scaling. Following this, the method plots the per unit power capability curves of both the FSC and the SDC (plotted on the same x and y axis). ...
p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on September 2023.
Abstract: Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simulator, thus enabling the study of real-time interactions of power electronics with large power systems. However, assembling an accurate scaled-down replica of an FSC with off-the-shelf laboratory SDCs is practically impossible due to a mismatch in per unit losses, as well as in the impedance of the L/LC/LCL filter. Consequently, the scaled-up power flow capability of SDCs differs from FSCs, restricting emulation to smaller regions of the four quadrants than those corresponding to the FSCs nominal active and reactive capacity. These PHIL test beds cannot be used to emulate FSCs demanding bidirectional active and reactive power flow. Any scaling method on SDCs, emulating the entire operation of FSCs, demands underutilisation of SDCs, reducing the advantages of PHIL tests. This paper, therefore, proposes a physics-informed scaling method that exploits power capability curves to emulate FSCs in all four quadrants of operation. This method is independent of SDC topology, filter type, and interfacing methods. A visual identification of the semiconductor device constraints bounding the emulation is also presented, utilizing the physics of converter control. A theoretical analysis of the proposed method is presented, followed by validation with MATLAB simulations and experimental tests using a 50 kVA SDC.</p
... 2) Novel harmonic-invariant scaling method (HISM) to exploit the base kVA rating of SDC for an accurate match with FSC. 3) Scaling method independent of the filter topology (L/LC/LCL) between the converter and the grid. 4) Simplified script, made publicly available at [21], to integrate with PHIL control code constrained by operating limits of the converter, available passive components in the laboratory, and a predefined error in normalized quantities. ...
p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on January 2023.
Abstract: Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early technology readiness levels. However, replicating the behavior of high-power systems with laboratory scaled-down converters (SDCs) can be complex. Inaccurate scaling of the SDCs coupled with an exclusive focus on instantaneous voltages and currents at the fundamental frequency can lead to PHIL results that are only partially relatable to the high-power systems under study. Test beds that fail to represent switching frequency harmonics cannot be used for studying harmonic penetration or loss characterization of large-scale converters. To tackle this issue, this paper proposes a harmonic-invariant scaling method (HISM) that exploits the VA rating of preexisting laboratory SDCs for more accurately replicating harmonic phenomena in a PHIL test bench. Firstly, a theoretical analysis of the proposed method is presented and, subsequently, the method is validated with MATLAB simulations and experimental tests.</p
... 2) Novel harmonic-invariant scaling method (HISM) to exploit the base kVA rating of SDC for an accurate match with FSC. 3) Scaling method independent of the filter topology (L/LC/LCL) between the converter and the grid. 4) Simplified script, made publicly available at [21], to integrate with PHIL control code constrained by operating limits of the converter, available passive components in the laboratory, and a predefined error in normalized quantities. ...
p>Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on January 2023.
Abstract: Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early technology readiness levels. However, replicating the behavior of high-power systems with laboratory scaled-down converters (SDCs) can be complex. Inaccurate scaling of the SDCs coupled with an exclusive focus on instantaneous voltages and currents at the fundamental frequency can lead to PHIL results that are only partially relatable to the high-power systems under study. Test beds that fail to represent switching frequency harmonics cannot be used for studying harmonic penetration or loss characterization of large-scale converters. To tackle this issue, this paper proposes a harmonic-invariant scaling method (HISM) that exploits the VA rating of preexisting laboratory SDCs for more accurately replicating harmonic phenomena in a PHIL test bench. Firstly, a theoretical analysis of the proposed method is presented and, subsequently, the method is validated with MATLAB simulations and experimental tests.</p
