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... The simulation time synchronization in this environment is similar to [5,6], with the difference that no specialized simulation kernel is required. In [14], authors present a distributed SystemC simulation environment for simulations involving geographically distributed intellectual property. Their main focus has been on geographical distribution and not on the simulation performance. ...
... Similar to [5,6,14], we use an application and model dependent number of sequential discrete event simulator processes in parallel. Each simulator is assigned a subset of the modules of a given TLM. ...
In recent years, transaction level modeling (TLM) has enabled designers to simulate complex embedded systems and SoCs, orders
of magnitude faster than simulation at the RTL. The increasing complexity of the systems on one hand, and availability of
low cost parallel processing resources on the other hand have motivated the development of parallel simulation environments
for TLMs. The existing simulation environments used for parallel simulation of TLMs are intended for general discrete event
models and do not take advantage of the specific properties of TLMs. The fine-grain synchronization and communication between
simulators in these environments can become a major impediment to the efficiency of the simulation environment. In this work,
we exploit the properties of temporally decoupled TLMs to increase the efficiency of parallel simulation. Our approach does
not require a special simulation kernel. We have implemented a parallel TLM simulation framework based on the publicly available
OSCI SystemC simulator. The framework is based on the communication interfaces proposed in the recent OSCI TLM 2 standard.
Our experimental results show the reduced synchronization overhead and improved simulation performance.
... There are other authors working on geographically distributed SystemC simulations [17]. Communications are made over Internet protocols and middleware such as SOAP, RMI or CORBA. ...
SystemC is a library that facilitates the development of Transaction Level Models (TLM). These models are composed of both
hardware and software components. This library allows designing and verifying hardware system components at a high level of
abstraction. This supports the development of complex systems. A real industry SystemC model usually contains a high number
of functional blocks which increase its simulation run time. SystemC executes only one process at any time, even if the hardware
supports execution of concurrent processes. In this paper we present a new methodology for distribution of the simulation
of complex models in a parallel computing system. We apply our own approach in a real industry SystemC model of a Power Line
Communication (PLC) network.
... Before concluding, a different approach is worth mentioning. In literature [50] some works pointed out the possibility to simulate different SystemC schedulers in parallel, each representing a "tile" of a very complex system. It is a really attractive concept, mostly within distributed systems, but in author's opinion it is still far from the reality of current platforms. ...
The Multi-Processors Systems on a chip (MPSoC) era is bringing about many new challenges for systems design in terms of computation and communication subsystems complexity. Interconnection systems became a pivotal component of the overall design, providing designers with advanced communication features such a split transactions, atomic operations and security adds-on. Momentum is building behind Networks on-chip (NoC) as future on-chip interconnection technology. Networks on-chip role isabout to take over shared busses whose scalability properties are already a major bottleneck for system design. Modeling of on-chip network is an exacting work; networks models must be fast, accurate and they have to sport standard interfaces. The main contributions of this work to networks on-chip design and implementation are: (1) the development of a brand new, full-edged network on-chip simulator based on OCCN, an open-source framework for NoC modeling developed within sourceforge available at http://occn.sourceforge.net, (2) the successfull integration of heterogeneous simulation environments in extremely complex platforms used to benchmark real STMicroelectronics SoC and (3) a thorough understanding and contribution to the design of STNoC—, the new interconnection technology developed within AST Grenoble lab of STMicroelectronics for future generation systems. The modeling environment has been used to benchmark two STMicroelectronics systems on-chip for High Definition digital Television (HDTV).
