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![SBCD transponder System-on-Chip Architecture [6].](profile/P-Toledo/publication/307578676/figure/fig2/AS:401995082027009@1472854504267/SBCD-transponder-System-on-Chip-Architecture-6.png)
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![Fig. 2. SBCD transponder System-on-Chip Architecture [6].](profile/P-Toledo/publication/307578676/figure/fig2/AS:401995082027009@1472854504267/SBCD-transponder-System-on-Chip-Architecture-6_Q320.jpg)
This work presents the design of a BPSK modulator suitable for a new satellite transponder for the Brazilian System of Data Collection (SBCD). The current generation of SBCD satellite transponders is in charge for frequency translation and retransmission of received signals from Data Collection Platforms (DCP) that are spread all over Brazilian ter...
Contexts in source publication
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... full proposed transponder is comprised by two main parts: the RF FrontEnd (including the receiver, transmitter and synthesizer) and DSP baseband (including carrier detection and synchronization and ARM M0 µprocessor for embedded applications). Fig. 2 shows the digital part of the SBCD transponder SoC published in [6]. The DCP signals received by SBCD satellites in UHF band are phase-modulated and relocated in frequency (S-band) to be transmitted back to ground station. As major advantage, this mixed signal SoC architecture implements a satellite transponder with local UHF signals ...
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... key functionality that differentiates this project [6] from current transponder generation is the insertion of a channel detection and a channel demodulation followed by a modula- tion process. As we can see in DSP part, Fig. 2, the channel detection is being performed using a Hanning-Window Fast Fourier Transform (FFT) along with a first demodulation and a filtering so that the system has the capability of to tracking down the presence of a signal from a DCP in a defined frequency bandwidth [5]. After and assuming that the channel frequency could have some ...
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... the DCP signals are detected and demodulated, the decoded messages are stored in an intermediate FIFO, denom- inated as Packet Bank Control in Fig. 2. The CPU (ARM M0) can check the messages stored and discard messages received with errors. The DCP signals are then phase-modulated and relocated in 2.267 GHz frequency (S-band) transmitting all information back to the ground stations. The adopted BPSK Modulator, as "SBCD Mod" in Fig. 2, architecture and its design is shown in the next ...
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... intermediate FIFO, denom- inated as Packet Bank Control in Fig. 2. The CPU (ARM M0) can check the messages stored and discard messages received with errors. The DCP signals are then phase-modulated and relocated in 2.267 GHz frequency (S-band) transmitting all information back to the ground stations. The adopted BPSK Modulator, as "SBCD Mod" in Fig. 2, architecture and its design is shown in the next section as main purpose of this ...
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... SBCD Modulator block, at top right of Fig. 2 and detailed in Fig. 3, is responsible for reconstructing a standard DCP message conforming to the SBCD format. There are up to 8 modulator channels operating at the same time, as illustrated in Fig. 4. The block communication is based on the Manchester Encoding, which represents each bit as a ...
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... output of all modulator blocks and noise generator must be combined in order to be applied to the automatic gain control and then to the phase modulator. This operation is made by the mixer block, which is presented in Figure 2. Its output should be normalized to the [-1,+1) interval and the gain of all re-modulated signals should be fixed and equivalent to a DCP signal with maximum power arriving at the satellite antenna (-112.34 ...
