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![Fig. 1. Ripple carry adder [5].](profile/Swaroop-Ghosh/publication/3226210/figure/fig7/AS:668473642455046@1536387944197/Ripple-carry-adder-5_Q320.jpg)
Design considerations for robustness with respect to variations and low-power operations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual- , etc., can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation-tolerant circuit desi...
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... the sake of simplicity, we choose a 4-b ripple carry adder, as shown in Fig. 1. Signals P 0 − P 3 (G 0 − G 3 ) are the propa- gate (generate) signals, whereas C i,0 (C o,1 − C o,3 ) are carry-in (carry-out) signals [5]. As evident, the path from carry-in to carry-out is critical and determines the frequency of operation of the adder. However, note that the critical path is activated only when C i,0 = 1, and at ...
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... circuit design is again based on CRISTA, i.e.; making the possible delay errors (under single-cycle operations) predictable and rare under parametric variations. We follow similar partitioning technique as dis- cussed in Section III-A. However, the sizing routine is modified to attain the path delay distribution, as shown by a cartoon in Fig. 10. It is easy to observe that this kind of delay distribution can allow the circuit to operate at two different lower voltages with small performance overhead. On obtaining this delay distribution, a temperature-adaptive DVS can be performed with the following conditions: 1) at normal temperatures, the circuit operates in single cycle ...
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... temperatures, the circuit operates in single cycle with nominal supply; 2) if the temperature violates threshold T REF1 , a lower supply V DDL1 is applied to push the critical cofactor to two-cycle operations; and 3) if temperature crosses threshold T REF2 (> T REF1 ), supply V DDL2 (< V DDL1 ) is applied so that the first noncritical cofactor (Fig. 10) also operates in two cycles. A thermal sensor can automatically make decision about the supplies (i.e., V DDH , V DDL1 , or V DDL2 ) that can be applied to the circuit. The activation of critical and first noncritical cofactors is predicted by ...
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... the temperature-adaptive design, the critical cofactor is downsized to meet slack S 1 ( Fig. 10) with respect to the clock period T c . Furthermore, one of the noncritical cofactors (i.e., first critical cofactor) is sized to meet a slack of S 2 . All other cofactors are upsized to meet the slack S 3 . The remaining steps are similar to Table I so the details are ...
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... architecture of CRISTA based temperature-adaptive pipeline (with three voltage domains) is shown in Fig. 11. Decoders D 11 , D 21 , and D 31 determine whether the critical cofactor of one of the stages is activated. Similarly, decoders D 12 , D 22 , and D 32 determine the activation of first noncritical cofactor of the stages. These two sets of decoders are ORed to predict the activation of critical cofactor and the first noncritical ...
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... failures are predicted ahead in time, and corrective action (i.e., two-cycle operation) is taken. However, the delay failures can occur when the supply is brought back from V DDL2 to V DDL1 or V DDL1 to V DDH . To avoid such situations, we place a few bits counter as delay element which extends the freeze signal for a few more cycles (as shown in Fig. 11). The proposed DVS technique can also be extended for N -stage pipeline (at the cost of extra AND and OR ...
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... target delay of the pipeline was 100 ps, and {V DDH , V DDL1 , V DDL2 } were found to be {1.0 V, 0.8 V, 0.75 V}. The thermal simulation result for our example pipeline circuit Fig. 11 is shown in Fig. 12. It can be observed that the tempera- ture rises from the ambient value and saturates after some time. At t = 4 × 10 5 ns, the temperature of the circuit crosses T REF1 , and the supply voltage is reduced to V DDL1 (i.e., 0.8 V) based on the sensor's output. As expected, the temperature reduces to approximately ...
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... target delay of the pipeline was 100 ps, and {V DDH , V DDL1 , V DDL2 } were found to be {1.0 V, 0.8 V, 0.75 V}. The thermal simulation result for our example pipeline circuit Fig. 11 is shown in Fig. 12. It can be observed that the tempera- ture rises from the ambient value and saturates after some time. At t = 4 × 10 5 ns, the temperature of the circuit crosses T REF1 , and the supply voltage is reduced to V DDL1 (i.e., 0.8 V) based on the sensor's output. As expected, the temperature reduces to approximately 100.7 • C after some ...
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... There is a minimum supply voltage Vdd min at which timing paths violate the set-up time; below such threshold, timing faults arise and logic errors propagate. A further reduction of the Vdd can m only be accomplished with modification of the circuit, e.g., reshaping the paths distribution via gate re-sizing [11] and/or timing-driven Boolean restructuring [12], or a relaxing of the timing constraint, e.g., by frequency scaling. Both solutions might have a negative impact on the energy efficiency. ...
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Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for an 128-bit multiplier, compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.0028 mean relative error. Additionally, we demonstrate the performance-energyquality (PEQ) trade-offs for different degrees of compression, achieved through configurable logic clustering. While evaluating the effectiveness of the proposed approach three case studies were set up. First, a Gaussian blur filter was designed, which demonstrated up to 80% energy reduction with a meagre loss of image quality. Second, we evaluate our approach in machine learning application using perceptron classifier, showed up to 74% energy reduction with negligible error rate. Third, the proposed multiplier designs were used in a power-constrained image processing application. We showed that SDLC can achieve 60x improvement in computation capability, with potential to be employed in ubiquitous systems.
... Prediction based elastic-clocking. The authors of [13] propose a design paradigm, called CRISTA, that implements AVOS under a desired frequency constraint. The basic idea is to isolate the most critical paths through a custom re-synthesis stage that reshapes the original paths distribution. ...
This paper introduces Approximate Error Detection-Correction (AED-C), an error management scheme suited to adaptive power management on error resilient applications. Inspired by the working principle of Approximate Computing, AED-C implements energy-accuracy scaling using the error detection coverage as a knob: a low error coverage accelerates supply voltage scaling thus to achieve larger energy savings at the cost of quality-of-result (QoR); a high error coverage lessens the voltage scaling leading to high QoR at the cost of weaker energy savings. The AED-C mechanism is built upon elastic timing monitors, Razor flip-flops augmented with a tunable detection window and hardened with the aid of a dynamic short-path padding technique. Simulations over a representative set of circuits provide a comparative analysis with the state-of-art. The collected results show AED-C substantially reduces the average energy-per-operation (up to 44.7% savings w.r.t. Razor-driven Adaptive Voltage Over-Scaling) and the area overhead (3.3% vs. 62.0%), still guaranteeing reasonable QoR. When applied to a real-life application, i.e., Forward Discrete Cosine Transform Unit (FDCT) integrated into a JPEG compressor, AED-C shows 51.9% energy savings (w.r.t. a baseline FDCT implementation) and a PSNR of 48.45 dB (w.r.t. baseline JPEG images).
