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This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in...
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... power consumption, modest phase noise specification, modest output frequency, differential quadrature outputs required) a ring oscillator based VCO is a suitable structure. Since quadra- ture outputs are required, an even number of differential delay cells is required. All the requirements could be met with the minimum number of two delay cells. Fig. 5 shows the implementation of a single delay cell. Transistors M1 essentially form an inverter. This structure was chosen since no DC current sources are needed which saves power consumption. Furthermore full rail-to-rail switching is employed which results in a better phase noise performance [14], [15]. Since no true fully differential ...
Citations
... The power consumption of the proposed receiver is only 1 mW when the differential lownoise amplifier works intermittently through the bias switch. Based on the 0.13 μm CMOS process, Helleputte et al. [61] proposed an integrated ultra-low-power analog front-end architecture for UWB pulse radio receivers, as shown in Figure 9e. A local oscillator is adopted to reduce the power consumption of pulse correlation, and the proposed receiver has a power consumption of 2.7 mW at a 39.0625 Mpulses/s pulse rate. ...
... Obviously, the mainstream fabrication process of UWB pulse radio receivers is 0.18 μm CMOS technology. Compared with other receivers, the 0.13 μm process adopted by Hellepute [61] can improve the performance, and reduce power consumption and chip area. The architecture proposed by Anis [59] has a high bandwidth, which can transmit highspeed signals in an indoor situation. ...
... The architecture proposed by Anis [59] has a high bandwidth, which can transmit highspeed signals in an indoor situation. Due to the sub-1 GHz operating bandwidth, the signal transmitted by the architectures [60,61] is a low-speed signal with a strong penetrating ability and wide range. Compared with other receivers, the architecture proposed by Medi [57] achieves lower power consumption and a higher maximum bit rate, which makes it suitable for high-speed data communication. ...
Ultra-wideband (UWB) technology has been applied in many fields, such as radar and indoor positioning, because of its advantages of having a high transmission rate, anti-multipath interference, and good concealment. In the UWB physical layer, the transmitting link, including an encoder and a pulse generator, is used to improve the anti-interference ability of the signal, while the receiving link, including a receiver and a decoder, can correct the error signal. Therefore, the performance of the UWB physical layer can obviously affect the speed and quality of UWB signal transmission. In this paper, the structure and performance of the codec and transceiver of the UWB physical layer are introduced and compared. In addition, some typical architectures and features are summarized and discussed, which provides a valuable reference and suggestions for the design of the UWB physical layer. Finally, the outlook of the UWB physical layer is presented: its development direction mainly includes high speed, low power consumption, and fewer hardware resources.
... The "dynamic range first" approach is so common that many engineers are, in fact, surprised to learn about entire application spaces that operate using only a few --or even just one --ADC bit. Examples of specialized wireless systems based on few bit ADCs include global positioning system (GPS) receivers [3]- [6]; radio astronomy [7], [8]; pulse Doppler radar [9]- [14], noise radar [15], [16], and next generation automotive radar [17]; low power [18]- [22], ultrawideband [23], [24], and impulse [25]- [29] communications; ultrawideband spectrum monitoring [30] and channel estimation [31], [32]; digital RF memory (DRFM) and electronic warfare (EW) receivers [33]- [39]; and even biological sensing and computation [40]- [43]. The motivations for restricting a receiver design to only a few bits can vary widely to include: maximizing sample rate [38], minimizing power dissipation [25], achieving insensitivity to clock jitter over long coherent integration times [9], [10], [44] and, perhaps most importantly, dramatically reducing digital processing throughput requirements in large scale systems [45]- [79]. ...
... Examples of specialized wireless systems based on few bit ADCs include global positioning system (GPS) receivers [3]- [6]; radio astronomy [7], [8]; pulse Doppler radar [9]- [14], noise radar [15], [16], and next generation automotive radar [17]; low power [18]- [22], ultrawideband [23], [24], and impulse [25]- [29] communications; ultrawideband spectrum monitoring [30] and channel estimation [31], [32]; digital RF memory (DRFM) and electronic warfare (EW) receivers [33]- [39]; and even biological sensing and computation [40]- [43]. The motivations for restricting a receiver design to only a few bits can vary widely to include: maximizing sample rate [38], minimizing power dissipation [25], achieving insensitivity to clock jitter over long coherent integration times [9], [10], [44] and, perhaps most importantly, dramatically reducing digital processing throughput requirements in large scale systems [45]- [79]. Most recently, interest in few bit receivers for 5G communications has exploded [46]- [78], both for millimeter wave phased arrays and for massive MIMO architectures. ...
Digitizing RF signals using few bit ADCs can provide system advantages in terms of reduced power dissipation, wider sampling bandwidth, and decreased demand for digital throughput. The diversity of established applications based on few bit ADCs, together with the recent surge of interest in the topic for 5G wireless communications and millimeter wave radar, have created a need for practical design guidance governing their use in general RF systems. This paper therefore summarizes the state of the art in few bit ADCs, comparing the dynamic range considerations involved with those of conventional RF receiver design. A simple analytic model for the monobit ADC is extended to multiple bits. Parametric analysis independent of sampling considerations and system-specific signal processing is used to illustrate the variation in ADC output signal-to-noise-and-distortion ratio (SNDR) vs. both the number of quantization bits and the input signal-to-noise ratio (SNR). At low and negative input SNR, increasing ADC resolution beyond 3-4 bits yields little advantage in output SNDR. Experiment confirms analytic predictions for the specific conditions under which the loss of signal fidelity due to quantization can be made negligible. In addition, parametric analysis of two-tone intermodulation distortion shows clear disadvantages to quantizing with < 4 bits in the presence of strong blockers. The results reported in this paper, which are general and independent of system application, can be used to customize the number of ADC bits in an RF system based on system-specific performance requirements for receiver dynamic range.
... As with any wireless communication system, in an LTE receiver, a variable-gain amplifier (VGA) is an indispensable building block and it maximizes the dynamic range of the communication links, where the variation in the received signal strength is significant due to channel fading [1]. The variable-gain function can be provided with discrete steps, then VGA is generally called as the programmable-gain amplifier (PGA), which demonstrates good linearity and noise performance [2][3][4][5]. However, systems like orthogonal frequency-division multiplexing (OFDM) and impulse radios require continuous gain control without any glitch [6]. ...
... Noise optimization is done for maximum gain conditions as will be explained later. Thus g m1,2 is much larger than g m3,4 , which makes g m3, 4 and so I n3,4 2 negligible in Eq. 5. If the circuit is designed in such a way that the bias current I M9,10 is much smaller than I M1,2,5,6 , I n9,10 2 can also be neglected. ...
In this study, a constant-bandwidth variable-gain amplifier (VGA) is presented for long-term evolution (LTE) receivers. The presented VGA’s description is given with a newly proposed exponential-current generator, and also the common-mode feedback and the DC-offset cancellation (DCOC) circuits. The proposed exponential current generator is based on the Taylor series approximation in such a way that it can be expanded to meet the required gain control range. The simulations are performed using the TSMC 180 nm process technology with Cadence Analog Virtuoso. The VGA has a 45 dB gain control range, 180 MHz bandwidth, 15.7 dB m the third-order input-intercept point for minimum gain and below 20 dB noise figure for maximum gain which makes it convenient for LTE receivers. The simulations also show that the bandwidth of the VGA is fairly constant over the control range. Monte Carlo simulations reveal that by using a DCOC circuit, the VGA provides 30 dB output offset rejection. The overall power consumption of the circuit is 9.1 mW under a 1.8 V power supply.
... As shown in Fig. 8, the outputs of the Hogge-modified PD (signals P an N) drive then the two switches of the charge pump (CP) so that the output current I CP takes three possible values (I REF , 0, -I REF ) depending on P and N states. The chosen topology for the charge pump is the one proposed in [20], which is based on the use of a reference current I REF copied through different branches thanks to current mirrors. At 1 Mbps, I REF has been taken equal to 1 lA so that the charge pump power consumption is ...
A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of −92 dBm for a 10⁻³ BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).
... However, even under this condition, waveform optimization can have better RMSE result. In the ultra wideband radar system, the unprecedented radio bandwidth provides advantages such as high precision of range estimation [110]. However, the extremely high sampling rate of ADC required in the UWB radar systems becomes a major challenge [111]. ...
The evolution of radar system developed from the adaptive radar to the radar with waveform diversity, and to the cognitive radar. Adaptive radar focuses more on the receiver adaptive capability. Waveform diversity deals with the probing radar waveforms according to some optimization criterion. The dominant feature of cognitive radar is cognition, which means the radar can actively learn about the environment. The whole radar system forms a dynamic closed feedback loop consisting of the transmitter, environment, and the receiver. Cognitive radar adjusts its system parameters and configurations in real-time to match its working environment and mission requirement. To build a cognitive engine, advanced mathematical tools like convex optimization are exploited to support waveform optimization. In order to provide a design philosophy and real-time demonstration of the concept of cognitive radar, an ultra-wideband multiple-input multiple-output cognitive radar testbed is proposed.
In an ultra wideband radar system, the unprecedented radio bandwidth provides advantages such as high-precision range estimation. However, the extremely high sampling rate of the analog-to-digital converter required in the radar system becomes a major challenge. Compressive sensing gives an opportunity to overcome this challenge, allowing the acquisition of signals at a much lower data rate than the Nyquist sampling rate. An algorithm is designed to get the time-of-arrival information from the sub-sampled echoed radar waveform. The effect of narrowband interference in the surveillance area is considered as well. A hardware architecture is proposed to fit into the special structure of the compressive sensing system. The proposed cognitive radar system can be considered as a large scale sensing system as well. Random matrix theory is applied to the statistical analysis of the radar dataset. Random matrix theory can achieve better per
... The linearity of this amplifier is determined by Rs 1 , where a smaller Rs 1 results in better linearity performance. In Fig. 18, a negative feedback through M 3 is employed (Helleputte et al. 2009), allowing Rs 1 to be reduced to g o1 /(g m1 g m3 ), greatly improving the linearity. The degeneration resistance Rs is controlled by 3-bit digital words to realize the 8-step gain control, with a minimum step size of 3 dB. ...
... Due to the nature of the impulse UWB radio, it provides a high-speed and highly secure uplink with a low-power and low-complexity transmitter implementation. Due to the ultrashort pulses used in UWB signaling, wideband UWB receivers on the other hand usually consume too much power for implementation in a battery-less operated device [9], [10]. Therefore, a traditional RF receiver such as UHF-RFID is applied as the downlink in the proposed system. ...
This paper discusses two antennas monolithically integrated on-chip to be used respectively for wireless powering and UWB transmission of a tag designed and fabricated in 0.18-μm CMOS technology. A multiturn loop-dipole structure with inductive and resistive stubs is chosen for both antennas. Using these on-chip antennas, the chip employs asymmetric communication links: at downlink, the tag captures the required supply wirelessly from the received RF signal transmitted by a reader and, for the uplink, ultra-wideband impulse-radio (UWB-IR), in the 3.1-10.6-GHz band, is employed instead of backscattering to achieve extremely low power and a high data rate up to 1 Mb/s. At downlink with the on-chip power-scavenging antenna and power-management unit circuitry properly designed, 7.5-cm powering distance has been achieved, which is a huge improvement in terms of operation distance compared with other reported tags with on-chip antenna. Also, 7-cm operating distance is achieved with the implemented on-chip UWB antenna. The tag can be powered up at all the three ISM bands of 915 MHz and 2.45 GHz, with off-chip antennas, and 5.8 GHz with the integrated on-chip antenna. The tag receives its clock and the commands wirelessly through the modulated RF powering-up signal. Measurement results show that the tag can operate up to 1 Mb/s data rate with a minimum input power of -19.41 dBm at 915-MHz band, corresponding to 15.7 m of operation range with an off-chip 0-dB gain antenna. This is a great improvement compared with conventional passive RFIDs in term of data rate and operation distance. The power consumption of the chip is measured to be just 16.6 μW at the clock frequency of 10 MHz at 1.2-V supply. In addition, in this paper, for the first time, the radiation pattern of an on-chip antenna at such a frequency is measured. The measurement shows that the antenna has an almost omnidirectional radiation pattern so that the chip's performance is less direction-depe-
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... Coherent receivers have severe specifications on time alignment that are difficult to fulfill by the synchronization circuit. This has been mitigated by the use of quadrature correlation2425262728293031, or more complex schemes323334 . When the signal is strong enough receivers can be noncoherent , which are usually simpler but more susceptible to noise. ...
Modern Ultra-Wide Band (UWB) regulations have recently been adopted worldwide allowing for unlicensed operation within 3.1 and 10.6 GHz, using an appropriate wideband signal format with a low Effective Isotropic Radiated Power (EIRP) level. UWB characteristics are suitable to transmit data using pulses instead of continuous-waves such as in narrowband radio links. It has the potential to be the right technology for high data-rate, low-power and short-to-medium range communication systems. We will focus on Impulse Radio-UWB (IR-UWB) systems and show their suitability for many different applications, including sensor networks, ad-hoc networks, cognitive radio, home networking, etc. We will also discuss the difficulties and challenges of designing IR-UWB systems. We present a tutorial overview of UWB regulations and usable signals. We present the existing standards and recommendations, and we review recently published results, highlighting trends in UWB transceiver power consumption and the impact of CMOS scaling on performance.
Les circuits de récupération d'horloge et de données sont nécessaires au bon fonctionnement de plusieurs systèmes de communication sans fil. Les travaux effectués dans le cadre de cette thèse concernent le développement de ces circuits avec d'une part la réalisation, en technologie HCMOS9 0,13 μm de STMICROELECTRONICS, de circuits CDR analogiques à 1 et 54 Mbit/s, et d'autre part, la mise en œuvre de fonctions CDR numériques programmables à bas débit. Un circuit CDR fonctionnant à plus bas débit (1 Mbit/s) a été conçu dans le cadre de la gestion d'énergie d'un récepteur ULB impulsionnel non cohérent. Ces deux structures ont été réalisées à l'aide de PLL analogiques du 3ème ordre. Un comparateur de phase adapté aux impulsions issues du détecteur d'énergie a été proposé dans cette étude. Les circuits ont ensuite été dimensionnés dans le but d'obtenir de très bonnes performances en termes de jitter et de consommation. En particulier, les performances mesurées (sous pointes) du circuit CDR à 1 Mbit/s permettent d'envisager une gestion d'énergie efficace (réduction de plus de 97% de la consommation du récepteur). Dans le cadre d'une chaîne de télémesure avion vers sol, deux circuits CDR numériques ont également été réalisés durant cette thèse. Une PLL numérique du second degré a été implémentée en vue de fournir des données et une horloge synchrone de celles-ci afin de piloter une chaîne SOQPSK entièrement numérique. Un circuit ELGS a également mis au point pour fonctionner au sein d'un récepteur PCM/FM.
