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Retraction etching steps in hot phosphoric acide, (a) Cross section while retraction etching, (b) Top view before retraction etching, (c) Top view after retraction etching.
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This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features to the formed. The pattern formed by conventional...
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Context 1
... nitride retraction etching has been done after step c in the fabrication scheme, Fig. 1. This step is shown in Fig. 6 in more detail. A thick silicon nitride retraction etching sequence has been shown in Fig. 6(a). Line of patterns depends on uniformity of silicon etching step before the retraction etching. As seen in Fig. 6(b), if there is local nonuniformity in patterning of silicon nitride caused by mask roughness, the final result of silicon ...
Context 2
... nitride retraction etching has been done after step c in the fabrication scheme, Fig. 1. This step is shown in Fig. 6 in more detail. A thick silicon nitride retraction etching sequence has been shown in Fig. 6(a). Line of patterns depends on uniformity of silicon etching step before the retraction etching. As seen in Fig. 6(b), if there is local nonuniformity in patterning of silicon nitride caused by mask roughness, the final result of silicon etching (line C C ′ − ) will lead to local uniformity after the silicon etching step. The reason is ...
Context 3
... nitride retraction etching has been done after step c in the fabrication scheme, Fig. 1. This step is shown in Fig. 6 in more detail. A thick silicon nitride retraction etching sequence has been shown in Fig. 6(a). Line of patterns depends on uniformity of silicon etching step before the retraction etching. As seen in Fig. 6(b), if there is local nonuniformity in patterning of silicon nitride caused by mask roughness, the final result of silicon etching (line C C ′ − ) will lead to local uniformity after the silicon etching step. The reason is the slow etching in <111>- direction [13]. ...
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Citations
Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated-based on a theoretical foundation including a statistical analysis-with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.
We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation.
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