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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSF...
Context in source publication
Context 1
... output waveform of 28T full adder cell is as shown in Figure 5. Figure 6 shows output waveform at 45nm. From the result Table 3 it is clear that performance of MOSFET based full adder in terms of the power and delay values are obtained and it can be concluded that there is an increase in the power and delay values of MOSFET based Full Adder at 45nm node and below due to short channel effect faced by MOSFET devices. ...Similar publications
In recent years, there has been a growing interest in energy efficient VLSI designs for portable devices. Full adder cell is one of the most widely used and important blocks of arithmetic units that are in many digital signal processors. The quest to reach low energy consumption, and high noise immunity in the nanoscale regime, directed this work f...
Citations
... DG FinFET-based full adder shows power, performance, temperature compatibility, and area optimization compared to the conventional full adder [94]. At 45 nm and 0.7 V VDD, the efficiency of DG FinFET full adder is 96.56% and that of CMOS-based full adder is only 52.30%, along with the reduction in propagation delay [95]. ...
... The design in [88] depicts the least power con-sumption out of all the full adders simulated at 16 nm node. Adders in [86,89,90,95], are simulated at 45 nm node. Design in [90] shows the least leakage power among all the adders. ...
... Design in [90] shows the least leakage power among all the adders. Full adder in [95] has the least propagation delay of 3.34 ps. PDP of the design in [90] simulated at a VDD of 0.7 V is the minimum out of the four adders simulated at 45 nm node. ...
Background
The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.
Objective
FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.
Methods
An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).
Results
The full adders using FinFETs show less leakage power and PDP. The AND-OR logic-based hybrid full adder using FinFETs shows the least energy consumption per switching. FinFET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.
Conclusion
MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultra-nanoscale regime.
... Adder is implemented using different logic style like pass transistor and transmission gate logic. In the proposed work, adder, multipliers, and shift register designs are explored with above said parameters [22][23]. ...
... Similarly, full adder circuits using MOSFETs evaluated as shown in Table 3. Therefore, FinFET is better replacement for MOSFET devices in future ICs [22]. ...
The VLSI Technology has been progressing significantly and the circuits which consume less power become major concern factor for designing todays ICs for Microprocessors and other various systems components. The Datapath is important part of a system. Adders, multipliers, and shift registers are the major components of data path unit of ALU. Almost all digital circuits and chips are made of MOSFET as the basic switching element. But same MOSFET suffers due to Short Channel Effects (SCEs) when scaled down to nano regime, which has promoted multigate device called FinFET. And this FinFET device overcomes the SCEs at technology nodes. In this paper 28T and 16T MOSFET and FinFET based full adders are designed. Using adders, 4x4 array multiplier is designed using both MOSFET and FinFET technology along with it Serial in Serial out shift register designs. The circuits designed based on MOSFET and FinFET are analyzed in terms of power and delay at various nodes. From the software characterization and analysis, it is understood that FinFET based circuits promise better performance at lower technology nodes like 22nm and 14nm than higher technology nodes in MOSFET like 250nm, 180nm, 90nm and 45nm. Hence FinFET becomes a promising device for future IC technology.
... In advanced systems and gadgets for quotidian use, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is popular for its better power availability produced with gradual scaling [12]. But further scaling of MOSFET presents obstacles in terms of enhanced Short Channel Effect (SCE) which reduces gate control, Oxide Breakdown, Velocity Saturation, Channel Length Modulation, Drain Induced Barrier Lowering (DIBL) etc. [13]. ...
Average power and delay are two essential aspects of measuring device performance in integrated circuits. The trade-off between the two for a full protected soft error tolerant latch has been observed for MOSFET and two different operating modes of FinFET across 45nm and 32nm technology nodes and a comprehensive comparative analysis has been provided in this paper. The simulations have been conducted on HSPICE simulator and the results show as much as 84% reduction in delay with almost 8 times increase in power consumption for SG FinFET operation. A 13% improvement in power delay product was observed using LP FinFET mode in comparison with prevalent MOSFET technology. The design consideration of device choice and operation mode was also discussed.
... The composite signal swing of the differential signal can be twice that of the single ended swing on the same power supply, increasing the signal-to-noise ratio [10][11][12]. The amplifier alternatively can be increased on the same power supply, distortion will be low, or a low power supply voltage can be used in order to provide same signal swing and lowering the power dissipation [13][14][15]. Besides that, an image rejection scheme and the use of Gilbert mixers are required to be fed from a differential source [16]. ...
span>In this paper, an inductively degenerated CMOS differential low noise amplifier circuit topology is presented. This low noise amplifier is intended to be used for wireless LAN application. The differential low noise amplifier proposed provide high gain, low noise and large superior out of band IIP3. The LNA is designed in 130 nm CMOS technology. Simulated results of gain and NF at 2.4GHz are 20.46 dB and 2.59 dB, respectively. While the simulated S<sub>11</sub> and S<sub>22</sub> are −11.18 dB and −9.49 dB, respectively. The IIP3 is −9.05 dBm. The LNA consumes 3.4 mW power from 1.2V supply. </span
