Fig 2 - uploaded by Sadiq Sait
Content may be subject to copyright.
Representation of logic design problem.

Representation of logic design problem.

Source publication
Article
Full-text available
In this paper, we employ fuzzified Simulated Evolution (SimE) Algorithm for combinational logic design. SimE algorithm consists of three steps: evaluation, selection and allocation. Multilevel Logic Based Goodness measure is designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization o...

Context in source publication

Context 1
... Î ÄÍ Ì ÁÇAE : outline of the SimE algorithm and Figure 2 is a representa- tion of the problem considered. ...

Similar publications

Article
Full-text available
We present a technique, termed clock- generating (CG) domino, for improving dual-output domino logic that reduces area, clock load, and power without in- creasing the delay. A delayed clock, generated from cer- tain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits in...
Article
Full-text available
Bayesian modeling method and slice anal-ysis techniques show good effect in cycle-accurate power analysis of combinational circuit. In this paper, we use vir-tual signal logical depth assignment to resolve the problem that signal loop can not be sliced in sequential circuits. With this method, we build cycle-accurate power model based on Bayesian i...
Article
Full-text available
This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re‐ordering circuitry at the input side. As a res...
Article
Full-text available
Bug-fixing in deeply embedded portions of the logic is typically accompanied by the post-facto addition to new assertions which cover the bug scenario. Formally verifying properties defined over such deeply embedded portions of the logic is challenging because formal methods do not scale to the size of the entire logic, and verifying the property o...
Conference Paper
Full-text available
While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, refer...