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Register-transfer Finite State Machine
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In this paper, we formally define an enhanced RTL semantics. This is intended to elevate the RTL design abstraction level and help bridge the HDL semantic gap among synthesis, simulation and formal verification tools. We define the enhanced semantics based on a new RTL++ language that supports pipelined operations using a new pipelined register var...
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Citations
... Description of partial design decisions are possible as well. However, multi-cycle and pipelined functional units are not supported [17]. ...
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.
... Communication between processes can also be accomplished through channels. Similar to the definition of register in [13], a channel can be regarded as that it consists of two buffers, one for storing its current value and the other for storing its new value. Each execution of a channel output statement generates a request to update the channel if the value of the expression is different from the current value of the channel. ...
As a system-level modelling language, SystemC possesses some new and interesting features such as delayed notifications, notification cancelling, notification overriding and delta-cycle. It is challenging to formalise SystemC. In this paper, we first select a kernel subset of SystemC and study its operational semantics. Based on the operational semantics we define a bisimulation relation, from which program equivalence is explored. Finally, we present a set of algebraic laws for the subset language, which can be proved based on the operational semantics model via bisimulation
... Pipelined signals have been suggested by Zhao and Gajski [ZG05]. It is interesting to note that they specically state that while they see the need for such a language feature, the could not locate a suitable HDL to embed it in. ...
... Recent publications like [ZG05] show that very basic features (seen from a signal processing perspective) are only now being suggested as HDL language features. Zhao and ...
... Gajski [ZG05] even state explicitly that no suitable platform for integration of the suggested features could be found. It seems therefore likely that further additional features to HDLs will be suggested and discussed in the near future as HDLs are used for modelling of increasingly complex algorithm implementations. ...
Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that functional languages are especially suitable for implementation of domain-specific languages, including HDLs. Casestudies examining the implementation complexity of HEP-specific language extensions to the functional HDCaml HDL will prove the viability of the suggested approach.
In this paper we formally define an operational semantics framework RTL++ for modeling behavioral RTL hardware IP. The semantics we define is neutral to existing HDLs and extends traditional sense RTL by natively supporting pipelined and multi-cycled operations with a unified register <i,l> variable type. We believe this formalization help to guide the design of new HDLs or extensions of existing HDLs in terms of elevating RTL design abstraction level and also bridging the current HDL semantic gap among synthesis, simulation and formal verification tools. The intra-module and inter-module execution of RTL++ semantics are specified in Plotkin-style structural operational semantics framework. An example of implementing the RTL++ extension of SystemC is presented along with experimental results showing the benefit of modeling in RTL++.
