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Register file and functional units

Register file and functional units

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Fig. 2. Interleaved memory system
Fig. 3. Vector register file
Fig. 4. Register file and functional units
Simple Vector Processor Modeled with VHDL
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Vector architectures have proven to be the best choice if we want to achieve high performance when executing numerical applications and multimedia. In this paper we describe a project whose main goal is to obtain a detailed description of a traditional vector processor using VHDL Hardware Description Language. This work will be very useful for dire...
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... units must generate results at the same rate of memory transactions, of course one result is produced every clock cycle. We are adding several functional units of integer type as shown in figure 4. ...

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