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This work investigates several approaches for implementing the OFDM functions of the fixed-WiMax standard on reconfigurable platforms. In the first phase, a custom RTL approach, using VHDL, is investigated. The approach shows the capability of a medium-size FPGA to accommodate the OFDM functions of a fixed-WiMax transceiver with only 50% occ...
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The Mobile WiMAX is an expectation from mobile users to give secured and seamless services. The ASN blindly forwards the MS details to its entire neighbor ASN (nASN) which introduce the overhead in the networks where there is no assurance that the MS moves to a particular BS (Base station). Again at the authentication phase, there is exchange of ke...
Citations
... Field Programmable Gate Arrays (FPGAs) offer the possibility of fully exploiting the algorithmic inherent parallelism for more demanding applications, such as massive content distribution, real-time military communications and online audio-clips trade. FPGAs are reconfigurable, flexible and physically secure devices with high computational capabilities and offer a fast design cycle [3]. Besides, FPGA-based implementation of data hiding systems seems to be an interesting option since its capacity for parallel processing could allow multi-channel processing. ...
... Hardware architectures can be designed at different abstraction levels, from RTL to higher ones using CAD tools. One of these tools commonly used in the industry is System Generator [3], which allows fast development in a friendly environment. Although an architecture designed using System Generator is not as efficient as a hand-made one, the difference in performance is not very significant such that System Generator becomes a very attractive design platform [3]. ...
... One of these tools commonly used in the industry is System Generator [3], which allows fast development in a friendly environment. Although an architecture designed using System Generator is not as efficient as a hand-made one, the difference in performance is not very significant such that System Generator becomes a very attractive design platform [3]. ...
One of the audio watermarking schemes with highest payload published to date is Fallahpour scheme, achieving about 3 kbps [1]. A keybased security improvement to this algorithm is proposed in [2] while significatively maintaining the payload. In this letter, a high throughput and compact hardware architecture for the Security Improved Fallahpour Audio Watermarking Scheme is proposed, demonstrating the suitability of this algorithm for real-time applications.
... As already mentioned, the automatically-produced HDL code is usually not as efficient as the custom hand-written HDL one. This difference is becoming a significant factor to be considered when stringent FPGA area utilization conditions apply or when performance and achievable clock frequencies do matter [7]. The modern FPGA devices and the corresponding synthesis tools seem to address the issues mentioned before. ...
The main purpose of steganography is to hide the presence of communication process. Transparency is referred to the ability to avoid suspicion about the existence of a secret message. Several steganographic applications, such as secret communications and multimedia fingerprinting, require a real-time multi-channel behavior. Custom hardware architectures offer the possibility of fully exploiting the inherent parallelism of this type of algorithms for more demanding applications. This paper presents an efficient hardware implementation of a low complexity steganographic system using digital images as host signal. Results of implementing the proposed hardware architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.
Future formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary. In this paper a system-on-a-chip design is proposed comprising of a general purpose processor and an IEEE 802.11 wireless network transceiver core, adapted to the space environment. Initial results on a novel implementation of the IEEE802.11a transmitter module are presented.
