Figure 1 - uploaded by Majid Ahmadi
Content may be subject to copyright.
Proposed word-parallel bit-serial multiplier in GF(2 6 )
Source publication
A new high speed word-parallel bit-serial finite field multiplier using a reordered normal basis is presented. The proposed multiplier is used for a class of finite fields in which there exists a type II optimal normal basis. FPGA implementation of the proposed multiplier with other similar multipliers are also presented. Architectural analysis and...
Context in source publication
Context 1
... follows from (1) By grouping different number of terms in the above formula different word size multipliers can be made. For the multiplier shown in figure 1 the word size is equal to 2. In this case half of the output terms are generated in the first clock cycle and the other half are added to the first part in the second clock cycle. Note that b 0 = 0 and output registers are initialized as zero and after w=2 clock cycles they should contain the product bits c 0 ,c 1 ,…,c 6 . ...
Similar publications
![Fig. 4. Earthquake damage. Source: Fot. Dr. Roger Hutchison/NGDC [17]](profile/Jakub-Bil/publication/314007308/figure/fig4/AS:465619792470021@1488023817876/Earthquake-damage-Source-Fot-Dr-Roger-Hutchison-NGDC-17_Q320.jpg)
![Fig. 5 Lorenz's Attractor. Source: [18] Ryc. 5 Atraktor Lorenza....](profile/Jakub-Bil/publication/314007308/figure/fig6/AS:668530819223561@1536401576849/Lorenzs-Attractor-Source-18-Ryc-5-Atraktor-Lorenza-Zrodlo-18_Q320.jpg)
The system of impact of an object of architecture is a non-linear dynamic system, which also makes it a chaotic deterministic system. If we introduce into the system all impacts and system agent functions possible to identify, we can propose an estimated simulation of the life cycle of the entire object over time.
Citations
... The word level serial input parallel output architecture from [11] is shown in the third row. The Fourth row presents the bit-serial word-parallel architecture proposed in [9]. The last row of the table presents our proposed architecture. ...
... As can be seen from the table the proposed Architecture has the best performance between all multipliers. Taking into account the approximations for area and delay, the average performance increase for the proposed architecture is equal to 35% and 60% for w = 16, 8 respectively, compared to W-P B-S [9] which has the second best performance. V. CONCLUSIONS A new high speed word level finite field multiplier using a reordered normal basis is presented. ...
Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered normal basis is presented. Proposed architecture has a very regular structure which makes it suitable for VLSI implemen- tation. Architectural complexity comparison shows that the new architecture has smaller critical path delay compared to other word level multipliers available in open literature at the cost of having moderately higher area complexity. The new architecture out performs all other similar proposals considering the product of area and delay as a measure of performance. I. INTRODUCTION
In this paper, an efficient high-speed architecture of Gaussian normal basis (GNB) multiplierover binary finite field GF(2m) is presented. The structure is constructed by using some regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. For the powers of 2 exponents, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed multiplier is examined in terms of area and time complexity based on its implementation on Virtex-4 field programmable gate array family and also its application specific integrated circuit design in 180 nm complementary metal-oxide-semiconductor technology. Comparison results with other structures of the GNB multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilisation.
A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid architecture of the proposed design provides designer the ability to set the trade off between area and delay during the design process.
Two high-speed bit-serial word-parallel or comb-style finite field multipliers are proposed in this paper. The first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type-II optimal normal basis exists. The proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same. The proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis. Field-programmable gate array (FPGA) implementation results of the proposed multipliers are compared to those of the previous methods using the same basis, which confirms that the proposed multipliers allow a much higher clock rate.
