Fig 3 - uploaded by Mahdi Taheri
Content may be subject to copyright.
Source publication
This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. We propose a deep pipelining S-box at the gate level in which a novel DMR technique is used for fault correction. The proposed fault-resilient technique is based on fault correction in DMR implementation (FC-DMR) of each S-box's combined with...
Similar publications
The Modular multilevel converters (MMCs) have excellent performance when operated with high modulation index such as the case of gird-connected converters in high voltage direct current (HVDC) system. Reliable and fault tolerant operation (FTO) of the system is very important in HVDC. A novel FTO algorithm under sub module failure without using any...
Citations
... As a case-study we analyze the effect on a AES S-box design. There exist many reported implementations for the S-box of AES considering varying design metrics such as power, area and delay for various applications [6]- [13]. Without loss of generality, the composite field based S-box in [6] is selected as a case study in this paper (see Fig. 1). ...
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of faulttolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability
... In this scheme, the same input data is processed through the same unit three times. The majority voter generates the output of TTR by the majority vote of these three consecutive processes [26][27]. ...
... i.e., (((2 2 ) 2 ) 2 ) → ((2 2 ) 2 ), ((2 2 ) 2 ) → (2 2 ), and (2 2 ) → (2), can be made using the irreducible polynomials of 2 + + , 2 + + and 2 + + 1, respectively. As shown in Fig. 1, the output of the S-box, i.e., Y, is obtained using the affine transformation after inverse transformation (δ -1 ) [27]. The Sbox is composed of the multiplications, squaring, and inversion all of which are over ( (2 2 ) 2 ). ...
This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault correction purposes. The newly introduced countermeasure is a fault correction scheme based on the DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage becomes high. The control unit holds the previous correct value in the output of our proposed DMR voter in the other pipeline stages as soon as it observes the value ‘1’ on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provides a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original S-box implementation.
... R-CFTA is the most robust and reliable architecture among others. A high-throughput fault-tolerant hardware implementation of AES S-box based on hybrid redundancy is proposed by authors in [28]. ...
Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROM-based S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of fault-tolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability.
