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... proposed full adder circuit combines the MCIT for the sum operation and the Boolean reduction technique for the carry operation. The sum and carry circuits were designed based on standard full adder sum and carry equations. In the multiplexing method, input B and its complement were used as the control signals of the sum circuit, as shown in Fig. 1. The two-input XOR and combinational circuits were developed using the multiplexing method [8]. The output node of the two- input multiplexer circuit is the differential node. According to equation (1), the sum circuit requires three inputs. The AB circuit is directly connected to input C . To avoid increasing the number of ...
Context 2
... =A(BC) (1) Carry = AB + C (A B) (2) The proposed adder circuit is shown in Fig. 1, contains 8 transistors and 4 inverters. The adder circuit uses the minimum length of wire and the proper arrangement of the circuit resulting in reducing the critical path. The adder circuit minimises the wire length by using a shorter connection to the common circuit of the sum and carry (AB). ...
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Citations
... The output node of the two-input multiplexer circuit is the differential node. MUX-12T (Ramana Murthy et al., 2011) circuit is designed by using multiplexing method and Boolean identities. After the simplification of Boolean identities, the equations of sum and carry are derived. ...
... The proposed full adder is compared with the other six existing adders in parametric analysis by using BSIM 4. The circuit layout capacitance versus leakage current of the adder circuit is shown in Fig. 4 (a). According to diffusion leakage concept [13], the proposed adder circuit gives low diffusion leakage current due to short critical path and proper arrangement of transistors. Thus the proposed adder gives lower leakage current when compared with the other existing six adder circuits in terms of varying load capacitance. ...
... The three different CSA circuits such as MUX-12T [14], MCIT-7T [15] and the proposed 6T [16] are used as full adder blocks in the feedback loop of the pipelined IIR filter recursive section along with the proposed pass-transistor logic delay units are schematized by using DSCH3 CAD tool. The proposed full adder based IIR filter and other two adder based IIR filter layouts are analyzed in 45nm feature size by using Microwind 3. The CSA circuit performance depends on the transistor count as well as design concept. ...
... Power dissipation of the proposed 6-T adder circuit and the other two filter circuits in Monte Carlo simulation is as shown in Fig. 4 (d) clearly indicate that the proposed filter design performance is better compared with the other two filter circuits. The effective capacitance for dynamic power consumption is as shown in (14). (14) where this capacitance can be divided by the total transistor width to find the effective capacitance per micron. ...
... The effective capacitance for dynamic power consumption is as shown in (14). (14) where this capacitance can be divided by the total transistor width to find the effective capacitance per micron. The proposed 6T IIR is designed with the regular arrangement of transistors and low critical path leads to low power dissipation compared with the other filter circuits. ...
In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.
... Computations in these devices need to be performed using low-power, area efficient circuits operating at greater speed. The design of high-speed and lowpower VLSI architectures needs efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption [1]. Addition is not only one of the widely used fundamental arithmetic operations but also forms the nucleus of many other useful operations such as subtraction, multiplication, and division. ...
... So enhancing the performance of the 1-bit full adder cell is the main design aspect. One way to achieve ultralow power is by running digital circuits in subthreshold mode [1]. Subthreshold current of an NMOSFET transistor occurs when the gate-tosource voltage (V GS ) of a transistor is lower than its threshold voltage (V TH ). ...
... The output node of the two-input multiplexer circuit is the differential node. MUX-12T [1] adder is designed by using multiplexing method and Boolean identities. The simplest way of approach to the A⊕B is designed according to the multiplexer method. ...
Addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper a 1-bit full adder cell which uses only six transistors has been proposed. In this design, three multi-plexers and one inverter are used to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay and power-delay product (PDP) are analyzed and compared with the existing adders using BSIM4 at 90 nm feature size. The results show that the proposed adder has both lower power consumption and low PDP value. The proposed full adder clearly outperforms other existing adders in its temperature sustainability behavior versus power dissi-pation, leakage current parameters. The low power and low transistor count makes the proposed 6T full adder cell a candidate for power-efficient applications.
... Computations in these devices need to be performed using low-power, area efficient circuits operating at greater speed. The design of high-speed and lowpower VLSI architectures needs efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption [1]. Addition is not only one of the widely used fundamental arithmetic operations but also forms the nucleus of many other useful operations such as subtraction, multiplication, and division. ...
... So enhancing the performance of the 1-bit full adder cell is the main design aspect. One way to achieve ultralow power is by running digital circuits in subthreshold mode [1]. Subthreshold current of an NMOSFET transistor occurs when the gate-tosource voltage (V GS ) of a transistor is lower than its threshold voltage (V TH ). ...
... The output node of the two-input multiplexer circuit is the differential node. MUX-12T [1] adder is designed by using multiplexing method and Boolean identities. The simplest way of approach to the A⊕B is designed according to the multiplexer method. ...
Addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper a 1-bit full adder cell which uses only six transistors has been proposed. In this design, three multiplexers and one inverter are used to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay and power-delay product (PDP) are analyzed and compared with the existing adders using BSIM4 at 90nm feature size. The results show that the proposed adder has both lower power consumption and low PDP value. The proposed full adder clearly outperforms other existing adders in its temperature sustainability behavior versus power dissipation, leakage current parameters. The low power and low transistor count makes the proposed 6T full adder cell a candidate for powerefficient applications.
Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.
This paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate the threshold voltage loss problem which is commonly encountered in Pass Transistor Logic (PTL) design. The proposed design successfully embeds the buffering circuit in the full adder design which helps the cell to operate at lower supply voltage compared with the other related existing designs. It also enhances the speed of the cascaded operation significantly while maintaining the performance edge in energy consumption. In the proposed design, the transistor count is minimized. For performance comparison, the proposed MUX-6T comparator (1-bit) is compared with four existing full adders based comparators using BSIM4 model parameters. The simulations are performed for 65nm process models indicate that the proposed design has lowest energy consumption along with the performance edge in both speed and energy consumption. The variants namely area and power of the proposed comparator is also compared with the published author designs to validate its suitability for low power and high speed mobile communication applications.
