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![QCA clock zones [26, 33]](publication/330876419/figure/fig4/AS:11431281178997630@1691144264728/QCA-clock-zones-26-33_Q320.jpg)
QCA is a hopeful technology in the field of nanotechnology that seems to suit well with signal processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The Multiply-Accumulator (MAC) unit is considered as one of the essential operation in Digital...
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Quantum-dot cellular automata (QCA) are prospective nanotechnology with striking performance to tackle the shortcomings of complementary metal-oxide-semiconductor (CMOS) transistor-based technology such as fabrication dimensions and switching speed. The demultiplexer, as a crucial component for the design of many logic circuits, comprises a circuit...
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... Four phases are switch, hold, release, and relax. QCA cell starts polarizing in the switch phase and completely polarized in the hold phase [14]. Binary data flows during the switch and hold phases. ...
... The layout shown in figure 7 is used for the fault analysis. The cell missing defect is possible for the cells 7, 8, 9, 10, 12, 13, and 16, while the cells 1, 2, 3, 4, 5, 6,11,14,15,17,18,19, and 20 causes cell addition defects. It is assumed that input and output cells are unchanged due to any type of fault defect. ...
... The least value of QCA layout cost is desirable. Layout cost is derived as provided in equation (14). ...
Quantum-dot cellular automata (QCA) nanotechnology is a suitable replacement for the widely accepted complementary metal oxide semiconductor (CMOS) technology. CMOS technology faces the issues of high-leakage current and non-scalability in the ultra-deep submicron (ultra-DSM) regime. It motivates the researchers to explore new technologies for further advancement of the field. QCA nanotechnology is energy-efficient technology and it overcomes the issues of CMOS technology in ultra-DSM regime. In this paper, a novel 3-input XOR structure is presented using QCA nanotechnology. The full adder and the full subtractor circuits based on the 3-input XOR gate are developed. A circuit for the full adder/subtractor nanostructure is proposed in the paper. All the proposed designs are optimal, fault-tolerant and single-layered. The proposed full adder contains only 21 QCA cells, while 22 QCA cells are required for the proposed full subtractor. The proposed full adder/subtractor structure consists of only 30 QCA cells. The proposed designs are compared with the existing designs for the number of QCA cells, total cell area, total covered area, area utilization, clock latency, QCA layout cost, and crossover requirement. The energy-efficient behaviour of the proposed circuits is calculated using the QCA Designer-E and the QCA Pro tools.
... ese benefits can make the proposed QCA method useful for image processing applications applied on portable communication devices where low power consumption is demanded in today's world. Recently, some efforts have been made towards the design of QCA logic circuits for image processing applications such as MAC operation [20], BinDCT [21], image steganography [22], morphological edge detection [23], thresholding [24], noise removal [25], and morphological erosion and dilation [26]. e above scenario motivates us to investigate a new low-power DCT architecture based on QCA technology. ...
Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential technique in image and video compression systems and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, Quantum-dot Cellular Automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Further, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool is applied to estimate the power dissipation of the proposed circuit. The Suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new
window of opportunity for low power image processing systems.
Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.
Digital signal processing (DSP) is used in computer processing to conduct different signal-processing tasks. The DSPs are used in the series numbers representing a continuous variable in a domain such as time, area, or frequency. The multiply-accumulate (MAC) unit is crucial in various DSP applications, including convolution, discrete cosine transform (DCT), Fourier Transform, etc. Thus, all DSPs contain a critical MAC unit in signal processing. The MAC unit conducts multiplication and accumulation operations for continuous and complicated DSP application processes. On the other hand, in the MAC structure, the stability of the circuit and the occupied area pose some significant challenges. However, high-performance quantum technology can easily overcome all the previous shortcomings. Hence, this paper suggests an efficient MAC for DSP applications using a Vedic multiplier, half adder, and accumulator based on quantum technology. All the proposed structures have used a single-layer layout without rotated cells. The suggested architecture is designed and validated based on the QCADesigner 2.0.3 tool. The findings revealed that all the developed circuits have a simple architecture with fewer quantum cells, optimal area, and low latency.
Following the considerable development of big data and the need for real-time information process-ing, the recent computing paradigm changed from centralized intelligence on cloud computing tothe distributed intelligence on Edge Computing. On the algorithm layer, Artificial Intelligence (AI) hasbeen applied in different areas related to intelligent-edge applications. In this type of application,consumption and speed present essential challenges when designing hardware-level architectureon the embedded systems. In particular, an Edge Computing System (ECS) must be an energyefficient, compact, and fast component integrated into edge devices. Miniaturization has been hap-pening at a steady pace for the last years. However, the MOS transistor size has been slowly reachingthe physical limit. In this paper, we propose a Quantum Cellular Automata clock-phase-based tech-nique for the design of the proposed ALU module. The obtained results using the QCA architecturedesigner exhibit better performances over the existing designs in terms of size, cell number, cost,latency, and power consumption. We have also used QCAPro software for power consumptionestimation. The results show the effectiveness of the design in terms of cost and power
This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular
Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU)
which presents a fundamental part in several digital integrated circuits. The classical implemen-
tation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS)
Technology presents several problems in terms of frequency, power consumption, surface and oth-
ers. The QCA technology offers several features such as ultralow power consumption, small size,
and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area
and high speed is proposed. The proposed design is based on a half-adder circuit and other logic
gates. These designs were tested and simulated using the freely known QCA Designer Tool version
2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms
of cell count, latency and power consumption, respectively compared to existing designs. The pro-
posed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the
RCA design. The proposed circuit present an optimization of 20% in term of energy consumption
compared to the existing PPA 4-bit Brent Kung Adder design.
This study demonstrates the development of an innovative [Formula: see text]-bit less power ripple carry incrementer (RCI) and decrementer (RCD) circuit, respectively, devised using quantum dot cellular automata (QCA). In order to increment or decrement two numbers, RCI and RCD are essential. With a revised configuration of the AND gate, half adder, and XOR gate circuit, the suggested ripple carry incrementer and decrementer circuits are realized. Modern designs for the XOR and half adder are contrasted with these freshly created ones. Circuits are designed using QCA designer 2.0.3. The 4-bit RCI, 8-bit RCI, and 16-bit RCI as well as 4-bit RCD, 8-bit RCD, and 16-bit RCD simulation results are compared to the theoretical findings.
