Figure - available from: IET Circuits, Devices & Systems
This content is subject to copyright. Terms and conditions apply.
Proposed 8‐bit serialised architecture of SEED Block Cipher (a) G Function, (b) FU Function and (c) Round FU, (d) The top‐level architecture
Source publication
This study presents an 8‐bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1‐bit registers flip‐flops (FFs) in the BASYS3 board, operates with an 8‐bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at...
Similar publications
![Fig. 5. GEMM core internal after adopting technique from [13]....](publication/366382440/figure/fig5/AS:11431281175407777@1689729919404/GEMM-core-internal-after-adopting-technique-from-13-Illustrated-systolic-tensor-array_Q320.jpg)
p>Practical deployment of convolutional neural net?work (CNN) and cryptography algorithm on constrained devices are challenging due to the huge computation and memory requirement. Developing separate hardware accelerator for AI and cryptography incur large area consumption, which is not desirable in many applications. This paper proposes a viable s...
Lightweight Cryptography (LWC) iswidely used to provide integrity, secrecy and authentication for the sensitive applications.However, the LWC is vulnerable to various constraints such as high-power consumption, time consumption, and hardware utilization and susceptible to the malicious attackers. In order to overcome this, a lightweight block ciphe...
![Figure 1. ANU-II cipher [8]](publication/361008525/figure/fig1/AS:11431281101412998@1669430799658/ANU-II-cipher-8_Q320.jpg)
Nowadays the number of embedded devices communicating over a network is increasing. Thus, the need for security appeared. Considering various constraints for the limited resources devices is very important. These constraints include power, memory, area and latency. A perfect environment for satisfying requirements of security in limited resources d...
![Fig. 5. GEMM core internal after adopting technique from [13]....](publication/366378760/figure/fig5/AS:11431281175435687@1689729918902/GEMM-core-internal-after-adopting-technique-from-13-Illustrated-systolic-tensor-array_Q320.jpg)
p>Practical deployment of convolutional neural net?work (CNN) and cryptography algorithm on constrained devices are challenging due to the huge computation and memory requirement. Developing separate hardware accelerator for AI and cryptography incur large area consumption, which is not desirable in many applications. This paper proposes a viable s...
Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field p...
Citations
... CURUPIRA-1, CURUPIRA-2, PUFFIN, XTEA and PRESENT) [7]. On other hand, many VHDL and FPGA developers modified many light weight cipher protocols such as cryptoprocessor design [8] and SEED block cipher [9]. ...
... The proposed module needs a set of op-codes to select multiple cryptographic modes. Therefore, the idea of duplication of the instruction set for 8051 was quoted [9,10,11]. Therefore, will modify the AVR by adding instruction switch called Instruction-Toggling-Switch (ITS) as shown in the figure (2). The dashed lines represent the added units. ...
... The set of VIs "CRY2B" consist of four VIs ("CRY21", " CRY22", "CRY23" and " CRY24") has op-codes "DD71h", "DD72", "DD73" and "DD74" respectively. They perform bit-rotation according to data representation in the figure (9). The nibble of selected key defines the number of shifted bits in one cycle (from 1 to 7 bits) within the outer bytes ( 11 , 12 , 13 , 14 , 24 , 34 ) and ( 44 , 43 , 42 , 41 , 31 , 21 ) of the matrix. ...
Nowadays, various wireless communication sensors, detectors and controllers (such as low-end IoT) are used all over the world. They are vulnerable to the threat of hackers and attackers. Such these attacks could lead to great danger to buildings, factories, or even lives. For this reason, multi-level data encryption is highly required. But it is difficult to run a complex encryption algorithm on these embedded systems because they have limited size, power, memory, and processor. Therefore, light block ciphers (LBC) are the best solution for this case. In this paper, a module capable of performing fast dynamic symmetric LBC (FDSLBC) will be designed based on the concept of dynamic data shuffling and exchange. Moreover, a modification proposal within a microcontroller family by this new module. This FDSLBC module is designed by VHDL to be controlled by various proposed cipher Vector Instructions (VIs). Each one of this VI capable to carry out a complete block cipher protocol during only one clock pulse. So, security system designers can use combinations of these VIs to create fast, robust, and dynamic systems in what is called cryptographic-instructions agility.
... Therefore, the better tradeoff between the security, power, area and speed is obtained by designing the lightweight block cipher [9]. Some of the examples of the lightweight ciphers are the STES [10], SEED [11], ANU [12], KLEIN [13], PRESENT [14], and KASUMI [15] and so on. From the different lightweight cipher, PRESENT block cipher is selected as an efficient algorithm due to its hardware efficiency and it also standardized by ISO/IEC 29192-2. ...
... The values of A1 − A2 and A3 − A4 are processed under XNOR operation, once the addition is completed. Eq. (11) shows the process of XNOR operation and sample XNOR operation between the pair of A1 − A2 is shown in Tab. 5. ...
Lightweight Cryptography (LWC) iswidely used to provide integrity, secrecy and authentication for the sensitive applications.However, the LWC is vulnerable to various constraints such as high-power consumption, time consumption, and hardware utilization and susceptible to the malicious attackers. In order to overcome this, a lightweight block cipher namely PRESENT architecture is proposed to provide the security against malicious attacks. The True Random Number Generator-Pseudo Random Number Generator (TRNG-PRNG) based key generation is proposed to generate the unpredictable
keys, being highly difficult to predict by the hackers. Moreover, the hardware utilization of PRESENT architecture is optimized using the Dual port Read Only Memory (DROM). The proposed PRESENT-TRNGPRNG architecture supports the 64-bit input with 80-bit of key value. The performance of the PRESENT-TRNG-PRNG architecture is evaluated by means of number of slice registers, flip flops, number of slices Look Up Table (LUT), number of logical elements, slices, bonded input/output block (IOB), frequency, power and delay. The input retrieval performances analyzed in this PRESENT-TRNG-PRNG architecture are Peak Signal to Noise Ratio (PSNR), Structural Similarity Index (SSIM) and Mean-Square Error (MSE). The PRESENT-TRNG-PRNG architecture is compared with three different existing PRESENT architectures such as PRESENT On-The-Fly (PERSENT-OTF), PRESENT Self-Test Structure (PRESENT-STS) and PRESENT-Round Keys (PRESENT-RK). The operating frequency of the PRESENT-TRNG-PRNG is 612.208 MHz for Virtex 5, which is high as
compared to the PRESENT-RK.
... Furthermore, if the Control Unit of each design, is not included in the area measurements, the use of allocated resources will be reduced by a factor equal to 30%. This is a great advantage, especially for constrained devices, and operation environments, as it has been also applied in other similar published works [14], [17]. ...
Alongside the rapid expansion of Internet of Things (IoT), and network evolution (5G, 6G technologies), comes the need for security of higher level and less hardware demanding modules. New cryptographic systems are developed, in order to satisfy the special needs of security, that have emerged in modern applications. In this paper, a novel lightweight data streaming system, is proposed, which operates in alternative modes. Each one of them, performs efficiently as one of three in total, stream ciphering modules. The operation of the proposed system, is based on reconfigurable logic. It aims at a lower hardware utilization and good performance, at the same time. In addition, in order to have a fair and detailed comparison, a second one design is also integrated and introduced. This one proposes a conventional architecture, consisting of the same three stream ciphering modes, implemented on the same device, as separate operation modules. The FPGA synthesis results prove that the proposed reconfigurable design achieves to minimize the area resources, from 18% to 30%, compared to the conventional one, while maintaining high performance values, for the supported modes.
Lightweight cryptography provides security to resource-constrained applications, such as embedded systems and Internet of Things (IoT) devices. This work explores an ultra-lightweight implementation of RC5 block cipher, via two levels of serialization. We also exploit a resource-sharing optimization technique for the data-dependent rotation (DDR) module, since it is the most computationally intensive component of the RC5 block cipher. We present two RC5 hardware structures: (i) an 8-bit serial RC5 architecture using a dual-part DDR unit; this design occupies only 54 slices on a Spartan-6 FPGA device and is 69% superior in terms of Throughput-per-Slice (TPS) compared to the smallest 8-bit AES FPGA implementation, (ii) a novel bit-serial RC5 architecture based on shift-register LUT (SRL) primitives; this design consumes only 20 Spartan-6 slices and shows 81% improvement in throughput performance at the expense of only 5% additional area resources compared to the smallest bit-serial AES design reported. The proposed DDR-based optimizations and efficient time scheduling make our proposed designs outperform most of the state-of-the-art lightweight block cipher designs in terms of hardware efficiency (with regard to TPS).
Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.
Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.
