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Process follow of 3D chip scale stacking with vertical via last TSV

Process follow of 3D chip scale stacking with vertical via last TSV

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Article
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3D WLCSP with via last TSV and UV laser releasable temporary bonding technologies is an ideal scheme to meet the increasing high performance, low cost and small-form-factor requirements. In present paper, we demonstrate a thin 3D WLCSP process using 8 inch wafers, and a number of critical process technologies were developed to realize the final 3D...

Citations

... With the continuous advancement of new infrastructure construction such as 5G, Internet of Things, artificial intelligence and wearable devices, integrated circuits (ICs) have encountered physical node failures according to the technical route of size reduction, and various bottlenecks in performance, power consumption, and area indicators [1][2][3]. As it has become difficult to meet the future development needs of the ICs industry by relying solely on size miniaturisation, industry has begun to realise the importance of realising the industrialisation of 3D integration [4]. ...
Article
The laser debonding process in advanced packaging has become a key technology for the debonding of ultra-thin wafers. However, improving the reliability of debonding and efficient removal of adhesive residues from thin and brittle devices remains challenging. Here, we fabricated bonding pairs formed by inorganic responsive layer, thermal buffer layer, and adhesive layer based on a structural design-oriented strategy. Experimental results showed that the thinned device wafers did not show any damage after laser debonding, and the residual adhesive film could be easily torn off. The response layer (a-Si:H) with high temperature resistance and corrosion resistance has strong photosensitivity under the action of ultraviolet laser with a wavelength of 355 nm, and rapidly decomposes to release H 2 and polysilicon nanoparticles. The thermal buffer layer is primarily intended to block the heat flow and compensate internal stress. The adhesive layer acts both as an adhesive during temporary bonding and as a barrier to laser-induced gas shock waves and plasma etching of device layers during debonding. This rational structural design contributes to improves the reliability of the laser debonding process and shows great potential for application in the next generation of thin device debonding.
... Wafer/chip stacked technology is one of the key technologies to realize 3D integration. Depending on whether the integration is performed at wafer or die level, there are three stacking options in 3D integration: wafer-to-wafer, chip-to-wafer and chip-to-chip [4,5]. At present, metal-to-metal direct bonding technology is an attractive option in the next generation of power devices and 3D IC technology, such as Au-Au, Cu-Cu or Al-Al [6][7][8][9]. ...
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An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance–voltage technique is proposed. First, an accurate high-frequency capacitance–voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance–voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.
Article
In this work, a low-temperature wafer-level bonding process at 150 °C was carried out on Si wafers containing 10 µm-sized microbumps based on the Cu-Sn-In ternary system. Thermodynamic study shows that addition of In enables low-melting temperature metals to reach liquid phase below In melting point (157 °C) and promotes rapid solidification of the intermetallic layer, which are beneficial for achieving low-temperature bonding. Microstructural observation shows high bonding quality with low amount of defect. SEM and TEM characterization concludes that a single-phase intermetallic formed in the bond and identified as Cu6(Sn,In)5 with a hexagonal lattice. Mechanical tensile test indicates that the bond has a mechanical tensile strength of 30 MPa, which are adequate for 3D heterogeneous integration.