Fig 8 - uploaded by Julien Frougier
Content may be subject to copyright.
Process flow and schematics of the key process steps of improved AS integration. A key difference is that AS is formed after MOL contacts (AS Late or AS-Late), in contrast to the conventional AS-Early flow in which AS is formed before MOL.
Source publication
We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimenta...
Context in source publication
Context 1
... overcome those challenges associated with the conventional AS, we have developed an improved AS integration. Fig. 8 depicts the basic process flow and structural schematics of the new scheme. Compared with the conventional AS-Early approach, a key feature of the new integration scheme is that the AS is created after the MOL process (referred as "AS Late, or AS-Late) [22]. In the AS-Late flow, the spacer remains solid during MOL SAC and COAG ...
Citations
... It was indicated that single event responses of FinFET may be significantly affected by ion hit angular, position and energy, supply voltage, device size and number of fins, technology node, and so on 3,[5][6][7] . With the aggressive shrinking of device dimensions, spacer configuration and permittivity play the dominant roles in overall device performance [8][9][10][11][12][13][14] . It has been indicated that the device performance in terms of SS, current drivability, drain induced barrier lowering (DIBL) could be improved using an optimized spacer configuration 13,14 . ...
The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO2 are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO2 spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.
... The transconductance (g m = dI DS /dV GS ) values for the NSHTs are plotted as a function of V GS and I DS per micron width in Fig. 8a and b, respectively. The g m values are observed to be relatively more significant for the optimized NSHTs than baseline NSHTs due to an increase in the overall gate capacitance [21]. The maximum g m value observed is 1.11 mS for optimized WS-NSHT. ...
This work proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer and an underlap region. A symmetric dual-k spacer structure and an undoped underlap region are incorporated into the baseline device to optimize it for better performance. The optimized NSHT exhibits an improvement of 54% in the onto off current ratio (I ON /I OFF) and 36% in the off current (I OFF) over the baseline NSHT of 5 nm node. The analog performance of the optimized NSHT is compared with the performance of the baseline NSHT device across the design space. The optimized NSHT, with L g /W g = 12 nm/120 nm, shows the largest transconductance (g m) value with a 6.7% increment compared to the baseline device. An increase of 4.9% in the maximum value of A v is obtained in optimized NSHT with L g /W g = 12 nm/15 nm, as compared to its baseline counterpart NSHT. Also, the intrinsic gain (A v) of optimized NSHT, with L g /W g = 12 nm/120 nm, shows a most significant improvement of 8.6% over its baseline counterpart NSHT. NSHT with L g /W g = 12 nm /120 nm has the highest value of unit-gain frequency (f T) for both optimized and baseline structures. Baseline NSHT shows higher f T values. NSHT with L g /W g = 12 nm/15 nm shows the highest gain frequency product (GFP). The optimized NSHT device gives a better analog performance in terms of gain (A v). However, the baseline NSHT device will serve the purpose better for analog applications requiring large f T and GFP values.
... The dielectric constant (= k) of air is 1 and it is much smaller than other dielectric materials (ex, SiO2's k = 3.9, SiN's k = 7). Therefore, we introduced the air spacer process to reduce the degradation of circuit characteristics caused by C MOL [21], [22]. Fig.12 shows a simplified cross-sectional view when an air gap was inserted into the spacer area. ...
... In this work, when analyzing the change when introducing the air-spacer process, it is assumed that the air spacer consists of 20% and 50% air pockets. According to [21], [22], the air pocket portion is 20% and 50% based on SiN (k = 7), and the air spacer's k is reduced to 3.3 and 1.65, respectively. As the capacitance decreases with the decreased value of k, the degradation of circuit performance due to C MOL is also improved. ...
With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back-end-of-line (BEOL) on the circuit performance. We constructed a process design kit (PDK) for path-finding to analyze the circuit layout in a 3nm technology node based on gate-all-around FET (GAA-FET). It consists of the spice model library that satisfies the 3nm power performance area (PPA) target, and the layout versus schematic (LVS), parasitic extraction (PEX) model that checks whether the layout and schematic match, extracts the RC values in the FEOL MOL and BEOL areas. Subsequently, the effect of the interconnection on complex logic circuits (RO, full adder) was confirmed using PDK. As a result of quantifying the effects of FEOL, MOL, and BEOL on the circuit, circuit degradation due to the RC of MOL and BEOL accounts for more than 60%. Furthermore, we introduced the air spacer process as a way to improve the circuit performance by reducing the C
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MOL</sub>
owing to the reduction in the dielectric constant of the spacer. When an air spacer is introduced, based on 9-stages FO1 INV RO with k = 7 at V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub>
= 0.7V, under iso-speed condition, the active power decreases by 30%, 35% when k is 3.3, 1.65, respectively. Under iso-power condition, frequency increases by 9%, 11% when k is 3.3, 1.65, respectively. And based on full adder with k = 7 at V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub>
= 0.7V, Under iso-speed conditions, the active power decreases by 47%, 58% when k is 3.3, 1.65, respectively. Under iso-power conditions, the delay decreases by 14%, 20% when k is 3.3, 1.65, respectively. PDP decreases by 22%, 32% when k is 3.3, 1.65, respectively. EDP decreases by 31%, 44% when k is 3.3, 1.65, respectively. In conclusion, in this work, we provide a guide for determining the BEOL load and developing an improved wiring process.
... Many reported literatures depict the usage of air-pockets as spacers (commonly known as air-spacers) to further increase the performance of the transistors and their applications in circuits, by reducing the gate parasitic capacitances [26][27][28][29][30][31][32]. NSTs can also incorporate air-pockets as inner spacers using the process steps explained in literature [33][34][35]. ...
... The g m for the NSTs increases with increase in W g /L g ratio of NST. The g m values are observed to be relatively smaller for the NST devices with the air-spacer than those for the NSTs with the low-k spacer, due to the decrease in the overall gate-capacitance [29]. The maximum g m value observed is 1.27 mS for WS-NST device with lowk spacer. ...
A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from the in-house ViennaPS simulation tool together with device and circuit simulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver. We apply our framework on two fabrication flows, when the air gap is created before and after the deposition of the first metal contacts layer. We observe that introducing the air gap inside the spacer results in an at-least 15% improvement in the ring oscillator’s performance, when the power is kept constant. Further improvements can be achieved by reducing the conformal layer thickness and increasing the sticking probability by increasing the chamber partial pressure or increasing the process temperature.
Through a comparative analysis of gate-all-around field-effect transistors (GAAFETs) with the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin shape on device performance is determined using the 3-D technology computer-aided design (TCAD) simulation. Moreover, this comparative study presents the most optimal taper angle in terms of various device figures of merits (FoMs) for a standard supply voltage (
${V}_{\text {DD}}$
) of 0.7 V and a low
${V}_{\text {DD}}$
of 0.35 V. Since FinFET of sub-3 nm is most affected by the short-channel effect (SCE), the vertical shape with the best electrostatic control is advantageous for dc and ac performances. On the other hand, in the case of GAAFETs, such as nanowire (NW) and nanosheet (NS), although vertical fin is the lowest dc performance due to the smallest effective width, we confirmed the best ac results due to the impact of capacitance gain. Furthermore, we demonstrated that NWFET and NSFET with straight shapes could achieve more than the frequency gain of
$2.2\times $
and
$1.2\times $
at the same power, respectively, compared to FinFETs in low
${V}_{\text {DD}}$
operation.
